FEDL87V2107-01
OKI Semiconductor
ML87V2107
3.1.3 Vertical Sync. Signal (OVS) Internal Generation Timing
In IVS reset synchronous generation mode, OVS occurs in field units in vertical direction mode as shown in Table
F3-1-1(4) from the position that is set in SVDL[10:0] (SUB:69h-bit[7:0],6Ah-bit[2:0]) in 0.5 line units of OHS
using the vertical Sync. signal (IVS) on the input side as the reference position.
In TRG reset synchronous generation mode and OCLK-dividing synchronous generation mode, OVS occurs in
frame units by division of the input clock signal of the internal OCLK using the frame cycle trigger signal as the
reference.
In OCLK-dividing synchronous generation mode, trigger signals are output from the TRG pin.
In TRG reset synchronous generation mode, an IC in OCLK-dividing synchronous generation mode and an IC in
TRG reset synchronous generation mode are synchronized by inputting from the TRG pin the trigger signals that
are output from the IC in OCLK-dividing synchronous generation mode.
The OVS polarity can be set in OVSIN.
The OHS generation starting phase can be set in SFINV.
• Timing of delay adjustment by SVDL[10:0]
OVS occurs using IVS (TRG) as the reference. By setting SVDL[10:0], the OVS generation position can be
adjusted in 0.5 line units of OHS. Consequently, a delay difference within about 0.5 line to 1 field can be set for
generation of OVS for IVS.
However, in IVS reset synchronous generation mode, when the delay adjustment value by SVDL[10:0] is set to
the IVS cycle or more, OVS does not occur. In TRG reset synchronous generation mode, OVS does not occur
when the delay adjustment value is set to one frame or more.
In OCLK-dividing synchronous generation mode, the delay adjustment function through SVDL[10:0] does not
occur.
[Delay adjustment amount] = SVDL[10:0] × [0.5 line period of OHS]
SVDL[10:0]=n: Delay adjustment
IVS
OVS
:IVS reference position
:OVS generation reset position
Figure F3-1-3(1) Horizontal Direction Delay Adjustment Timing
(IVS Reset Synchronous Generation Mode)
SVDL[10:0]=n: Delay adjustment
TRG
OVS
:OVS generation reset position
:TRG reference position
Figure F3-1-3(2) Horizontal Direction Delay Adjustment Timing
(TRG Reset Synchronous Generation Mode)
The OVS pulse width, which can be set by VSYM (SUB:6Eh-bit[0]), is standard (2.5H:625lines, 3H:525lines) by
setting VSYM = 0 and 1.5H (625/525 lines common) by setting VSYM = 1.
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