FEDL87V2107-01
OKI Semiconductor
ML87V2107
FUNCTIONAL DESCRIPTION
1. Input/Output
1.1 Input Memory Control
The ML87V2107 accesses data to the input data frame memory by generating a line access type memory control
signal from Sync. signals of the IVS and IHS pin inputs or the Sync. signals separated from SAV and EAV, and
achieves noise reduction of frame/field/line adaptation recursive type.
1.1.1 Input Control Mode Settings
This IC offers a choice of six input control modes, shown below, which can be selected by setting either the
external setting pin mode (IRMON = 0 (SUB: 40h–bit [7]) or internal register mode (IRMON = 1).
In ITU-R BT.656 input mode, the IC checks the mode by measuring the horizontal direction blanking period
(between EAV and SAV) of the timing reference code of the input data (YI[7:0]) and automatically sets VMD[0]
by setting APN656 = 1 (SUB: 41h-bit[2]).
The value that is set can be read from PNID (SUB:47h-bit[5]).
Table F1-1-1 (1) Input Control Mode Setting Allocation
VMD
HMD
IRMON
[1]
[0]
[1]
[0]
MODE 0
MODE 1
0
1
SUB:40h-bit[1]
SUB:40h-bit[1]
SUB:40h-bit[3]
SUB:40h-bit[3]
(External pin)
SUB:40h-bit[0]
(External pin)
SUB:40h-bit[2]
Table F1-1-1 (2) Input Control Mode Settings
VMD
[1]
HMD
Standard clock
frequency fICLK
[MHz]
Number of
valid lines
Standard pixels
per line
Vertical mode
Valid pixels
[0] [1]
[0]
0
1
0
0
0
0
0
0
1
625/50Hz 2:1
525/60Hz 2:1
625/50Hz 2:1
288(304)
243(254)
288(304)
13.5/27
13.5/27
14.75/29.5
864
858
944
720
720
768
0
0
0
12.272727/
24.545454
14.75/29.5
1
0
1
0
1
1
1
0
0
525/60Hz 2:1
625/50Hz 2:1
525/60Hz 2:1
243(254)
288(304)
243(254)
780
944
910
640
768
768
0
0
0
14.31818/
28.63636
Other than above
Test modes
*: ( ) indicates only ITU-RBT.656 input/output mode can be selected.
The input system internal clock frequency fIICLK is as follows:
16-bit input mode: fIICLK = fICLK
8-bit input mode/ITU-R BT.656 mode: fIICLK = fICLK/2
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