KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
5.1. FIFO control register(FCR)
The FCR is a write-only register at the same address as the IIR. FCR enables FIFO, sets the trigger level of the
receiver FIFO, and selects the type of DMA signaling.
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Bit 0 : FCR0 enables transmit and receiver FIFOs. All bytes in both FIFOs can be cleared by clearing this bit.
Data is cleared automatically from the FIFOs when changing from the FIFO mode to the 16C550 mode and
vice versa. Programming of other FCR bits is enabled by setting this bit.
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Bit 1 : When set, FCR1 clears all bytes in the receiver FIFO and resets its counter. This does not clear the shift
register.
Bit 2 : When set, FRC2 clears all bytes in the transmitter FIFO and resets its counter. This does not clear the
shift register.
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Bit 3 : When set, FRC3 changes RXRDY# and TXRDY# from mode 0 to mode 1 if FCR0 is set.
Bit 4, 5 : Reserved for the future use.
Bit 6, 7 : FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt. (see Table 1).
Table 1. Receiver FIFO Trigger Level
BIT
Receiver FIFO
Trigger Level
7
0
0
1
1
6
0
1
0
1
01
04
08
14
* FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled.
1. LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is reset.
2. Receiver line status interrupt(IIR = 06) has higher priority than the receive data available interrupt(IIR = 04).
3. Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.
4. Receive data available indicator(IIR=04) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.
The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are enabled.
1. When the following conditions exist, a FIFO character time-out interrupt occurs.
a. Minimum of one character in FIFO.
b. Last received serial character is longer than four continuous previous character times ago. (If two stop bits
are programmed, the second one is included in the time delay. Only the first stop bit is checked by the
UART.)
c. The last CPU of the FIFO read is more than four continuous character times earlier.
2. By using the XTAL1 input for a clock signal, the character times can be calculated. The delay is proportional to
the baud rate.
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KODENSHI [ KODENSHI KOREA CORP. ]
