KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
5.3. Line Status Register
This register provides status information to the CPU concerning the data transfer.
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Bit 0 : Data Ready(DR) indicator. Bit 0 is set to a logic 1 whenever a complete incoming character has been received and transferred into
the Receiver Buffer Register or the FIFO. This bit is cleared by reading all of the data in the Receiver Buffer Register of the FIFO.
Bit 1 : Overrun Error(OE) indicator. Bit 1 indicates that data in the Receiver Buffer Register was not read by the CPU before the next
character was transferred into the Receiver Buffer Register, thereby destroying the previous character. This bit is set to a logic 1 when
overrun occurs and cleared whenever the CPU reads the contents of the Line Status Register. If the FIFO mode data continues to fill the
FIFO beyond the trigger level, an overrun error will occur only after the FIFO is full and the next character has been completely received
in the shift register. OE is indicated to the CPU as soon as it happens. The character in the shift register is overwritten, but it is not
transferred to the FIFO.
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Bit 2 : Parity Error indicator. Bit 2 is set to a logic 1 upon detection of a parity error and is reset to a logic 0 whenever CPU reads the
contents of the Line Status Register. In the FIFO mode, this error is revealed to CPU when its associated character is at the top of the
FIFO.
Bit 3 : Framing Error indicator. Bit 3 indicates that the received character did not have a valid stop bit. This bit is set to a logic 1
whenever the stop bit following the last data bit or parity bit is detected as a logic 0 bit. It is reset to a logic 0 whenever CPU reads the
contents of the Line Status Register. In the FIFO mode, this error is revealed to CPU when its associated character is at the top of the
FIFO. When this error has been detected, CPU assumes it due to a next start bit, so it samples this start bit twice and the take the data.
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Bit 4 : Break Interrupt indicator. Bit 4 is set to a logic 1 when the received data input is held in the spacing state for longer than a full
word transmission time (start bit + data bits + parity bit + stop bits). The BI indicator is reset to a logic 0 whenever the CPU reads the
contents of the Line Status Register. In the FIFO mode, this error is revealed to CPU when its associated character is at the top of the
FIFO. When break occurs, only one zero character is loaded into the FIFO. The next character transfer is enabled after SIN goes HIGH
and receives the next start bit.
Bit 5 : Transmitter holding register empty(THRE) indicator. Bit 5 indicates that the UART is ready to take a new character for
transmission. In addition, this bit causes the UART to issue an interrupt to the CPU when the Transmit Holding Register Empty interrupt
enable is set to HIGH. This bit is set to a logic 1 when a character is transferred from the Transmitter Holding Register into the
Transmitter shift register. And it is reset to a logic 0 when the CPU transfers data to the Transmitter Holding Register. In the FIFO mode,
this bit is set to a logic 1 when the XMIT FIFO is empty, and is reset to a logic 0 when at least one byte is written to the XMIT FIFO.
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Bit 6 : Transmitter Empty indicator. This bit is set when the Transmitter Holding Register and Transmitter Shift Register are both empty,
and reset to a logic 0 when the THR contains a data character. In the FIFO mode, it is set to a logic 1 when the both the Transmitter FIFO
and the Transmitter Shift Register are empty.
Bit 7 : In the 16C550 mode, this bit is a 0. In the FIFO mode it is set to a logic 1 when it contains at least one error such as parity error,
framing error or break error. This bit is reset to a logic 0 when the CPU reads the Line Status Register and there exists no error.
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KODENSHI [ KODENSHI KOREA CORP. ]
