KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
3. Signal Description
NAME
A0
A1
A2
PIN NO.
I/O
DESCRIPTION
34 (48)†
33 (47)
32 (46)
Register select pins. A0, A1, and A2 three inputs are used to select the register
of the UART during read and write operations.
I
I
CS0#, CS1# 16,20 (28, 33)
CS2#, CS3# 50,54 (68, 73)
Chip Select. Each CSx# enables read and write operations to its respective
channel.
CTS0#,
CTS1#
11,25 (23, 38)
I
Clear to send. CTSx# is a modem status signal. Its status can be known by
reading bit 4 of the modem status register. CTS# does not affect the transmitor
receive operation.
CTS2, CTS3# 45,59 (63, 78)
D7~D3,
D2~D0
66~68(15~11) I/O Data Bus. Eight data lines with 3-state outputs provide a bidirectional path for data,
1~ 5 (9~7)
control, and status information between the KK16C554 and the CPU. D0 is the LSB.
DCD0#,
DCD1#
DCD2#,
DCD3#
DSR0#,
DSR1#
DSR2#,
DSR3#
Data Carrier Detect. A low on DCDx# indicates the carrier has been
detected by the modem. Its condition can be known by reading bit 7 of
the modem status register.
9,27 (19, 42)
43, 61 (59, 2)
I
I
10,26 (22, 39)
44,60 (62, 79)
Data set ready. DSRx# is a modem status signal. The condition of DSRx# can
be checked by reading the Bit 5 of the modem status register. DSR# does not
affect the transmit or receive operation.
DTR0#,
DTR1#
DTR2#,
DTR3#
Data Terminal Ready. DTRx# is an output that indicates to a modem or data set that
the UART is ready to establish communications. Setting the DTR bit of the modem
control register activates it. DTRx# is placed in inactive state either as a result of the
master reset during loop mode operation or clearing bit 0 of the modem control
register.
12, 24(24, 37)
46, 58(64,77)
O
GND
6, 23 (16,36)
40, 57 (56,76)
signal and power ground
Interrupt normal. INTN# in conjunction with bit 3 of the modem status register
and affects operation of the four interrupts (INT0~INT3).
INTN#
Low or
Float
Operation Of Interrupts
Interrupts are enabled according to the state of OUT2 (MCR bit 3).
When the MCR bit 3 is cleared, the 3-state interrupt output of that
UART is in the high Z state. When MCR bit 3 is set, the interrupt
output of the UART is enabled.
INTN#
65 (6)
I
I
High
Interrupts are always activated.
INT0, INT1 15,21(27,34)
INT2, INT3 19,55(67,74)
External interrupt output. When activated, INTx output informs CPU that UART has
an interrupt to be serviced.
IOR#
52 (70)
Read strobe. A low level on IOR# transfers the contents of the KK16C554 data bus to
the external CPU bus.
2
5
KODENSHI [ KODENSHI KOREA CORP. ]
