KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
3. The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received. This occurs
when there has been no time-out interrupt.
4. A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.
Transmit interrupts occurs as follows when the transmitter and transmit FIFO interrupts are enabled (FCR=0, IER=1).
1. When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR=02) occurs. The interrupt is
cleared when the transmitter holding register is written to or the IIR is read. 1 to 16 characters can be written to
the transmit FIFO when servicing this interrupt.
2. The transmitter FIFO empty indicators are delayed one character time minus the last stop bit time whenever the
following occurs.
THRE=1, and there has not been a minimum of two bytes at the same time in transmit FIFO since the last
THRE=1. The first transmitter interrupt after changing FCR0 is immediate, however, assuming it is enabled.
Receiver FIFO trigger level and character time-out interrupts have the same priority as the receive data available
interrupt.
The transmitter holding register empty interrupt has the same priority as the transmitter FIFO empty interrupt.
5.2. Line Control Register
The format of the data character is controlled by the LCR.
z
z
z
z
Bit 0, 1 : LCR0 and LCR1 are word length select bits. (see Figure 1)
Bit 2 : LCR2 is the stop bit select bit. The receiver always checks for one stop bit.
Bit 3 : LCR3 is the parity enable bit. When LCR3 is set, a parity bit is generated and checked.
Bit 4 : LCR4 is the even parity select bit. When LCR3 and this bit is set, even parity is generated and checked.
When LCR3 is set and this bit is cleared, odd parity is selected.
z
z
Bit 5 : LCR5 is the stick parity select bit. When LCR3 and this bit is set, the transmission and the reception of
a parity bit is forced to an opposite state from the value of LCR4. Clearing this bit disenables the stick parity.
Bit 6 : LCR6 is a break control bit. When this bit is set, the serial outputs TXDxs are forced to ‘0’. The break
control bit acts only on the serial output and does not affect the transmitter logic. If the following sequence is
used, no invalid characters are transmitted because of the break.
1. Load a zero byte in response to the transmitter holding register empty(THRE) status indicator.
2. The next THRE signal in the response of the set the break.
3. Wait for the transmitter to be idle, when transmitter empty status signal is set (TEMT=1) and then clear
the break, and start the normal transmission.
z
Bit 7 : LCR7 is the divisor latch access bit(DLAB). This bit must be set to access the divisor latches DLL and
DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the
Receiver Buffer Register, the Transmitter Holding Register, or the Interrupt Enable Register.
7
5
KODENSHI [ KODENSHI KOREA CORP. ]
