KK16C554PL/KK16C554TQ
QUAD-UART
ASYNCHRONOUS COMMUNICATIONS ELEMENT
5. Register Description
ADDRESS
REGISTER
REGISTER ADDRESS
MNEMONIC
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
RBR
Data bit Data bit 6
7 (MSB)
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
(LSB)
(read only)
THR
Data bit Data bit 6
7
Data bit 5
Data bit 4
Data bit 3
Bit 3
Data bit 2
Bit 2
Data bit 1
Bit 1
Data bit 0
(write only)
0†
1†
1
DLL
DLM
IER
Bit 7
Bit 15
0
Bit 6
Bit 14
0
Bit 5
Bit 13
0
Bit 4
Bit 12
0
Bit 0
Bit 11
Bit 10
Bit 9
Bit 8
(EDSSI)
Enable
modem
status
(ERLSI)
Enable
(ETBEI)
Enable
(ERBI)
Enable
receiver
line status
interrupt
Transmitte received
r
data
interrupt
Holding
register
empty
interrupt
Receiver
available
interrupt
Receiver
Trigger
(MSB)
Receiver
Trigger
(LSB)
Reserved
0
Reserved
0
DMA
Transmit
FIFO
2
2
3
FCR
mode
FIFO reset FIFO reset enable
(write only)
select
Interrupt‡
FIFOs‡
FIFOs‡
Interrupt
Interrupt
0
if
IIR
Enabled
Enabled
ID Bit (3)
ID Bit (2)
ID Bit (1)
interrupt
pending
(read only)
(DLAB)
Divisor
latch
Set break
Stick
(EPS)
Even
(PEN)
Parity
Enable
(STB)
(WLSB1)
(WLSB0)
Word
LCR
MCR
LSR
Parity
Number of Word
parity
select
Stop bits
length
length
access
bit
select bit 1 select bit 0
Loop
OUT2
Enable
external
interrupt
(INT)
Reserved
(RTS)
(DTR)
4
5
6
0
0
0
Request to Data
Send
terminal
ready
Error in
receiver
FIFO
(TEMT)
(THRE)
(BI)
(FE)
(PE)
(OE)
(DR)
Transmitte Transmitte Break
Framing
Error
Parity
Error
Overrun
error
Data ready
r registers
empty
r holding interrupt
register
empty
(DCD)
Data
(RI)
(DSR)
Data set
Ready
(CTS)
Clear to
Send
(∆DCD)
(TERI)
(∆DSR)
(∆CTS)
MSR
SCR
Ring
Delta data Trailing
Delta data Delta clear
carrier
detect
indicator
carrier
detect
Edge ring set ready to send
indicator
Bit 2
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
† DLAB = 1
‡ This bit is always in a low state when FIFO is disabled.
5
5
KODENSHI [ KODENSHI KOREA CORP. ]
