ESMT
Command Truth Table
COMMAND
M13S256328A
A11~A9,
A7~A0
CKEn-1 CKEn
DM BA0,1
A8/AP
Note
CS RAS CAS
WE
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
X
X
OP CODE
OP CODE
1,2
1,2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
X
X
3
3
3
Entry
Self
L
H
X
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
Refresh
Exit
L
Bank Active & Row Addr.
H
X
X
V
V
Row Address
4
4
Read &
Column
Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
Column
Address
H
H
X
X
L
L
H
H
L
L
H
L
4
Write &
Column
Address
Column
Address
X
V
4,6
7
H
Burst Stop
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank Selection
All Banks
V
X
L
X
Precharge
H
5
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
L
H
L
X
X
X
Active Power Down
X
Exit
X
H
L
Entry
H
Precharge Power Down
Mode
X
H
L
Exit
L
H
H
H
X
X
V
X
DM
X
X
X
8
H
L
X
H
X
H
X
H
No Operation Command
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
1. OP Code: Operand Code. A0~A11 & BA0~BA1 : Program keys. (@EMRS/MRS)
2. EMRS/MRS can be issued only at all banks precharge state.
A new command can be issued 1 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”..
Auto/self refresh can be issued only at all banks precharge state.
4. BA0~BA1 : Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank B is selected.
If BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
5. If A8/AP is “High” at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2 8/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
