ESMT
M13S256328A
AC Operating Test Conditions
Parameter
Value
Unit
V
Input reference voltage for clock (VREF
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (VIH/VIL)
)
0.5*VDDQ
1.5
V
1.0
V/ns
V
VREF+0.35/VREF-0.35
Input timing measurement reference level
Output timing reference level
VREF
VTT
V
V
AC Timing Parameter & Specifications
(VDD = 2.3V~2.7V, VDDQ=2.3V~2.7V, TA =0°C to 70°C )(Note)
-5
Symbol
Parameter
min
7.5
5.0
5.0
max
15
CL2
CL2.5
CL3
tCK
ns
ns
Clock Period
10
10
tAC
-0.65
+0.65
Access time from CLK/ CLK
CLK high-level width
tCH
tCL
tDQSCK
tDQSS
0.45
0.45
-0.65
0.85
0.55
0.55
tCK
tCK
ns
CLK low-level width
Data strobe edge to clock edge
+0.65
1.15
Clock to first rising edge of DQS delay
tCK
Data-in and DM setup time (to DQS)
tDS
0.5
-
ns
Data-in and DM hold time (to DQS)
tDH
tDIPW
tIS
0.5
1.75
1.0
1.0
2.2
0.4
0.4
0.2
0.2
-
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
DQ and DM input pulse width (for each input)
-
Input setup time
-
Input hold time
tIH
-
-
Control and Address input pulse width
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
tIPW
tDQSH
tDQSL
tDSS
tDSH
0.6
0.6
-
-
Data strobe edge to output data edge
tDQSQ
tHZ
-
-
0.4
ns
ns
Data-out high-impedance window from
CLK/ CLK
+0.7
Data-out low-impedance window from
CLK/ CLK
tLZ
-0.7
+0.7
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2
6/47
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
