EM785830AA
8-bit Micro-controller
For PLL clock = 895.658kHz ~ 14.3MHz (CLK2~CLK0 = 001 ~ 111)
ADCLK1 ADCLK0
Sampling rate
74.6K
Operation voltage
>=3.5V
0
0
1
1
0
1
0
1
37.4K
18.7K
9.3K
>=3.0V
>=2.5V
>=2.5V
For PLL clock = 447.829kHz (CLK2~CLK0 = 000)
ADCLK1 ADCLK0
Sampling rate
37.4K
Operation voltage
>=3.0V
0
0
1
1
0
1
0
1
18.7K
9.3K
4.7K
>=3.0V
>=2.5V
>=2.5V
This is a CMOS multi-channel 10-bit successive approximation A/D converter.
Features
74.6kHz maximum conversion speed at 5V.
Adjusted full scale input
External reference voltage input or internal(VDD) reference voltage
4 analog inputs multiplexed into one A/D converter
Power down mode for power saving
A/D conversion complete interrupt
Interrupt register, A/D control and status register, and A/D data register
Programmable
divider
ADC output
fpll
fadc
Divider
Nx
10-bit
ADC
fs
PLL
1/Mx
ADCLK1~ADCLK0
ENPLL
CLK2 ~ CLK0
Fig.9 ADC voltage control logic
fpll
Mx
fs
fadcon = fadc / 12
Nx = 1
Nx = 2
Nx = 4
Nx = 8
14.331MHz
10.747MHz
7.165MHz
3.582MHz
1.791MHz
895.658kHz
447.829kHz
16
12
8
4
2
895.658kHz
895.658kHz
895.658kHz
895.658kHz
895.658kHz
895.658kHz
447.829kHz
74.638kHz
74.638kHz
74.638kHz
74.638kHz
74.638kHz
74.638kHz
37.391kHz
37.391kHz
37.391kHz
37.391kHz
37.391kHz
37.391kHz
37.391kHz
18.659khz
18.659khz
18.659khz
18.659khz
18.659khz
18.659khz
18.659khz
9.329kHz
9.329kHz
9.329kHz
9.329kHz
9.329kHz
9.329kHz
9.329kHz
4.665kHz
1
1
Bit 5 ~ Bit 7(IN0~ IN2) : Input channel selection of AD converter
These two bits can choose one of three AD input.
IN2
IN1
IN0
Input
Pin
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-
-
Not select
Not select
P62
AD3
AD4
AD5
AD6
-
P63
P64
P65
Not select
Not select
-
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* This specification is subject to be changed without notice.
23
12/1/2004 V1.6