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C9820BYB 参数 Datasheet PDF下载

C9820BYB图片预览
型号: C9820BYB
PDF下载: 下载PDF文件 查看货源
内容描述: [Processor Specific Clock Generator, CMOS, PDSO24, 0.150 INCH, SSOP-24]
分类和应用: 时钟光电二极管外围集成电路晶体
文件页数/大小: 17 页 / 147 K
品牌: CYPRESS [ CYPRESS ]
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C9820  
Direct Rambus Clock Generator  
Preliminary  
Power Management Functions (Cont.)  
In the “power down” mode, the device is completely powered down for minimum power dissipation. This mode is used in  
conjunction with the power down modes of the RDRAMs and RAC.  
The device has three operating states: normal, Clock off and powerdown. In normal mode, the clock source is on, and  
the output is enabled. In Clock off mode, the clock source is on, but the output is disabled (StopB asserted). In  
powerdown mode, the device is powered down with the control signal PwrDnB equal to 0. the control signals Mult0,  
Mult1, S0, and S1 must be stable before power is applied to the device, and can only be changed in power-down mode  
(PwrDnB=0).  
Power Management Modes  
State  
Normal  
PwrDnB  
StopB  
1
1
0
1
0
Clock Off  
Powerdown  
X
Table 6: Control Signals for Clock Source States  
Upon applying power to the device, the device can enter any state, depending on the settings of the control signals,  
PwrDnB and StopB. the clock source output need not be glitch-free during state transitions.  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571  
http://www.imicorp.com  
Rev.1.3  
9/7/1999  
Page 7 of 17