C9820
Direct Rambus Clock Generator
Preliminary
State Transitions Timing Diagrams
Powerdown Exit and Entry
tP O W E R O N
PwrDnB
Clk/ClkB
tP O W E R U P
Figure:
6
Output Enable Control
tO N
tSTOP
StopB
tC L K O N
tCLKOFF
tCLKSETL
Clk/ClkB
Clock output settled within 50 pS of
the phase before disabled.
Output clock not
specified, glitches
may occur.
Clock enabled and
glitch free
Figure:
7
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.3
9/7/1999
Page 9 of 17