C9820
Direct Rambus Clock Generator
Preliminary
System Clock Configuration
Figure 3 shows the clocking configuration for an example Direct Rambus subsystem. The configuration shows the
interconnection of the system clock source, the C9820, and the clock signals of a memory controller ASIC. The ASIC
contains the RAC, the Rambus Memory Controller protocol engine (RMC), and logic to support synchronizing the
Channel clock with the controller clock (This diagram represents the differential clocks as a single Busclk wire).
S0/S1/S2 STOPB
C9820
Phase
Align
Refclk
PLL
C9801
Busclk
D
RAC
RMC
Pclk
M
N
4
DLL
Gear
Synclk
Ratio
Logic
Figure: 3 DDLL System Architecture
This configuration achieves frequency-lock between the controller and Rambus Channel clocks (Pclk and Synclk). these
clock signals are matched and phase-aligned at the RMC/RAC boundary in order to allow data transfers to occur across
this boundary without additional latency.
The main clock source drives the system clock (Pclk) to the ASIC, and also drives the reference clock (Refclk) to the
C9820. Refclk is not the same frequency as Pclk. A PLL inside the C9820 multiplies Refclk to generate the desired
frequency for Busclk. Busclk is driven on the Rambus Channel through a terminated transmission line. At the mid-point
of the Channel, the RAC senses Busclk using its own DLL for clock alignment, followed by a fixed divide-by-4 circuit that
generates SynClk.
Pclk is the clock used in the Rambus memory controller (RMC) in the ASIC. SynClk is the clock used at the ASIC
interface of the RAC. the C9820 together with the Gear Ratio Logic enables the controller to exchange data directly
from the Pclk domain to the SynClk domain without incurring additional latency for synchronization. In general, Pclk and
SynClk can run at different frequencies, so the Gear Ratio Logic must select the appropriate M and N dividers such that
the frequencies of Pclk/M and SynClkN are equal. In one example, Pclk = 133 MHz and SynClk = 100 MHz, and M = 4
while N = 3, giving Pclk/M = SynClk/N = 33 MHz.
The ASIC drives the output clocks, Pclk and SynClk/N from the Gear Ratio Logic to the C9820 Phase Detector inputs.
The routing of the Pclk/M and SynClk/N signal traces must be matched in impedance and propagation delay on the
ASIC as well as on the board. These signals are not part of the Rambus Channel and their routing must be matched by
board designers.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.3
9/7/1999
Page 3 of 17
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