C9820
Direct Rambus Clock Generator
Preliminary
Selection Logic (Cont.)
Mode
Normal
Clk Stop
StopB
Clk
ClkB
1
0
PAclk
VX,STOP
PAclkB
VX,STOP
Table 3: Clk Stop Mode Selection
Table 3 shows the logic for enabling the clock outputs, using the StopB input signal. When StopB is high, the DRCG is
in its normal mode, and Clk and ClkB are complementary outputs following the Phase Aligner output (PAclk). When
StopB is low, the DRCG is in the Clk Stop mode, the output drivers are both disabled (set to Hi-Z), and the Clk and ClkB
outputs both drive DC voltages (VX,STOP) as given in Table 11. The level of VX,STOP is set by internal resistor dividers.
Mode
Normal
S0
0
S1
0
S2
0
Bypclk (Int.)
Clk
PAclk
PLLclk
Refclk
-
ClkB
Gnd
PAclkB
Bypass
1
0
0
PLLclk
PLLclkB
Test
1
1
0
Refclk
RefclkB
Vendor Test A
Vendor Test B
Reserved
0
0
1
-
-
-
-
-
1
0
1
-
-
-
1
1
1
-
Output Test (OE)
0
1
X
Hi-Z
Hi-Z
Table 4: Bypass and Test Mode Selection
Power Management Functions
Mode
Normal
PwrDnB
Clk
PAclk
Gnd
ClkB
PAclkB
Gnd
1
0
PowerDown
Table 5: Powerdown Mode Selection
Table 5 shows the logic for selecting the Powerdown mode, using the PwrDnB input signal. PwrDnB is active low
(enabled when 0). When PwrDnB is disabled, the DRCG is in its normal mode. When PwrDnB is enabled, the DRCG is
put into a powered-off state, and the Clk and ClkB outputs are both low (ground).
The device is able to turn off the Rambus Channel clock to minimize power for mobile and other power-sensitive
applications. In the “clock off” mode, the device remains on while the output is disabled, allowing fast transitions
between the clock-off and clock-on states. This mode could be used in conjunction with the Nap mode of the RDRAMs
and Rambus ASIC Cell (RAC). When output clocks are in a power down mode they are driven to and held at a logic low
level by the device.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
http://www.imicorp.com
Rev.1.3
9/7/1999
Page 6 of 17
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