PRELIMINARY
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Power Management Timing
Latency
Signal
CS#
Signal State
No. of rising edges of free
running PCI CLOCK (PCIF)
0 (disabled)
1
1
1 (enabled)
PD#
1 (cold start/normal operation)
0 (power down)
3 mS
1
NOTES:
1. Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable
goes low/high to the first valid clock comes out of the device.
Spectrum Spread Clocking
Non -Spread
Reduction
Spread
Spectrum Analysis
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07046 Rev. **
5/03/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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