PRELIMINARY
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Frequency Selection Table
Outputs
CPU
Descriptions
48-24M/TS#
SEL
PCI
48M
48/24M
at Power UP
66/100
All Outputs Tri-State
66 MHz
0
1
1
0
0
0
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
66.66 MHz
33.33 MHz
48 MHz
48 MHz
7.16 MHz
24/48 MHz
24/48 MHz
7.16/3.58 MHz
100 MHz
100.00 MHz 33.33 MHz
Test Mode
7.16 MHz
2.38 MHz
Power Management Functions
PS#
X
CS#
X
PD#
0
CPU
LOW
LOW
ON
48M
LOW
ON
PCI
LOW
ON
PCI_F
LOW
ON
VCOs
OFF
ON
1
0
1
0
1
X
ON
LOW
ON
ON
CS# is an input clock synthesizer. It is used to turn off the CPU clocks for low power operation. CS# is asserted
asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU Clock)
and must be internally synchronized to the external PCI_F output. All other clocks will continue to run while the CPU
clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to
guarantee that the high pulse width is a full pulse. CPU clock on latency need to be 2 or 3 CPU clocks periods in time
and CPU clock off latency needs to be 2 or 3 CPU clocks periods in time.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07046 Rev. **
5/03/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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