PRELIMINARY
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Product Features
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Supplies:
2 Ref clocks
2 Host (CPU) clocks
1 free running and 5 PCI Clocks
1 48MHz fixed clock
1 48 or 24 MHz fixed clock
Separate supply pins for mixed (3.3/2.5V)
voltage application.
100 or 66 MHz CPU clock operation
-1.5% Spread Spectrum modulation for
reducing EMI
Rich Power Management Functions.
28-pin SSOP & TSSOP packages for minimum
board space.
Frequency Table
SEL 100/66#
0
1
CPU Clock
66.66 MHz
100.00 MHz
PCI Clock
33.33 MHz
33.33 MHz
Block Diagram
SEL48#
Pin Configuration
REF2
VDDR
XIN
XOUT
OSC
SS#
REF1
SEL48#
PLL
48-24M
48-24M/TS#
VDDC
SEL100/66#
CS#
PD#
PS#
SS#
PLL
CPU (1,2)
PCI_F
VDDP
VSS
XIN
XOUT
PCI_F
PCI1
PCI2
VSS
VDDP
PCI3
PCI4
PCI5
VDDF
48M
48-24/TS#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDR
REF/SEL48#
REF1/SS#
VDDC
CPU1
CPU2
VSS
VSS
PS#
VDD
CS#
PD#
SEL100/66#
VSS
PCI (1:3)
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07046 Rev. **
5/03/2001
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