PRELIMINARY
C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Pin Description
PIN No.
2
Pin Name
PWR
VDD
I/O
I
TYPE
XTAL4
Description
On-chip reference oscillator input pin. Requires either an
external parallel resonant crystal (nominally 14.318 MHz) or
externally generated reference signal
XIN
3
VDD
O
XTAL4
O-chip reference oscillator output pin. Drives an external
parallel resonant crystal (14.318 MHz) when an externally
generated reference signal is used.
XOUT
19
23, 24
17
18
16
-
P
O
I
I
I
PWR
C100S
INP3U
INP3U
INP3
3.3 volt power supply for core logic.
Clock outputs. CPU frequency table specified on page 1.
Powers down device when LOW
When signal is LOW, stops CPU clocks in low state.
Frequency select input pins. See frequency select table on
page 1. NO INTERNAL PULLUP RESISTOR IS PROVIDED
BY DEVICE
VDD
CPU (1,2)
PD#
CS#
SEL100/66#
VDDC
-
-
-
25
4
-
P
O
PWR
P100S
2.5V power for CPU and Host clock outputs.
Free running PCI clock 3.3V. Does not stop when PS# is at a
logic LOW level
VDDC
PCI_F
VDDP
5,6,9,
10,11
20
VDDP
O
P100S
PCI output clocks. See frequency table of page 1.
PCI(1:5)
-
-
I
P
INP3U
PWR
When signal is LOW, stops all PCI clocks in low state.
3.3 Volt power supply pins for free running PCI clock output
buffer.
PS#
VDDP
8
13
14
VDDF
VDDF
O
I/O
U48
Fixed 48 MHz clock.
48M
48-24M/TS#
U48BU Power up selectable 48 or 24 MHz clock. If strapped LOW at
powerup causes the devices outputs to be tri-stated until the
next power up sequence occurs.
26
27
VDDR
VDDR
I/O
I/O
U48BU At power up this pin determines if the device’s spread
spectrum modulation feature is enabled or disabled. After
power up this pin becomes a reference clock output. A 0 (logic
low) enables SSCG and a 1 (logic high) disables SSCG.
U48BU At power up this pin determine the frequency of the clock at pin
14. If it is LOW, the clock will be 48 MHz, if HIGH the clock will
be 24 MHz. After power up this pin will become a reference
clock output.
REF1/SS#
REF2/SEL48
#
12
1, 7, 15,
21, 22
28
-
-
P
P
PWR
PWR
Power for fixed clock output buffer.
Ground pins for device.
VDDF
VSS
-
P
PWR
Power for Reference Oscillator output buffer.
VDDR
Notes
1. INP3U pins have internal pullup resistors that will guarantee to a logic1 (high) level if no connection is made to the
device’s pin. INP3 pins do not contain this function and must be electrically connected to VDD or VSS by external
circuitry to ensure a valid logic 1 or 0 is sensed.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07046 Rev. **
5/03/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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