PRELIMINARY
C9641
133 MHz Clock Generator for ALI 1641 Chipset Systems
Vdd
Strapping Resistor Options:
The power up bidirectional pins have a large value pull-
up each (250KΩ), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
3mS settling time), then it is recommended to use an
external Pullup (Rup) in order to insure a high
Rup
50K
C9641
Rd
Load
Bidirectional
selection. In this case, the designer may choose one of
two configurations, see Fig. 3A and Fig. 3B.
JP1
JUMPER
Fig. 3A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
Fig.3A
Rdn
5K
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in
Fig.4A. Please note the selection resistors (Rup, and
Rdn) are placed before the Damping resistor (Rd)
close to the pin.
JP2
Vdd
3 Way Jumper
Fig. 3B represent a single resistor 10KΩ connected to a
3 way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
Rsel
10K
C9641
Rd
Load
Bidirectional
Fig.3B
Power Management Functions
If the “Mode” pin (pin 27) is strapped to a logic 0 at power up, the power management pins will be enabled. Power
Management on this device is controlled by CPU_STP# (pin19), PCI_STP# (pin20), PWR_DN# (pin21), and AGP_STP#
(pin22).
When CPU_STP# is forced low, all CPU signals are synchronously (no glitch) disabled in a low state. The CPU clocks
do not modulate stop, they will toggle one to three complete cycles before stopping on the falling edge, regardless of the
number of cycles it completes, it will stop before the next PCI_F rising edge occurs. This is to ensure synchronous
stopping after a full cycle without any glitches. When CPU_STP# is released to high, the CPU clocks are synchronously
re-enabled. The clocks will wait the equivalent of one to three cycles after CPU_STP# is asserted high then will start
toggling on the rising edge. Regardless of the number of cycles it completes, it will start before the next PCI_F rising
edge occurs. This also is to ensure a synchronous start of a full clock cycle.
When PCI_STP# is forced low, only PCI(1:5) signals are synchronously disabled in a low state. These signals will
complete one full cycle before stopping on the following falling edge. PCI_F is still running. When PCI_STP# is released
to high, PCI(1:5) are synchronously re-enabled after one full PCI_F cycle latency.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07037 Rev. **
5/02/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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