PRELIMINARY
C9641
133 MHz Clock Generator for ALI 1641 Chipset Systems
Byte 0: Functionality & Frequency Select Register (default = 0)
Bit
Description
CPU SDRAM
@Pup
Bit
AGP
PCI
7
6
5
4
(FS3) (FS2) (FS1) (FS0)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.82
100.23
66.82
133.64
66.82
100.23
100.23
133.64
90.03
100.23
100.23
66.82
100.23
133.64
133.64
66.82
66.8
33.40
66.8
66.8
66.8
66.8
66.8
66.8
66.8
60.0
63.4
70.0
82.4
59.8
63.2
69.8
73.1
33.40
33.40
33.40
33.40
33.34
33.40
33.40
30.01
31.67
35.00
41.2
(4:7)
133.64
90.03
Note 1, 3
95.02
126.35
139.71
109.99
119.75
95.02
105.00
109.99
119.75
126.35
139.71
146.22
29.94
31.59
34.93
36.56
105.00
146.22
Bit3 0 = Frequency is selected by hardware select, latched inputs (pins 1, 11 and 48)
1 = Frequency is selected by Bit 4:7
0
Bit2 00 = +/- 0.5% Center Spread Spectrum
01 = Down Spread Spectrum 0 to –0.5%
Bit1 10 = Spread Spectrum modulator off
11 = Tristate all outputs
00
Bit0 1 = 48_24#MHz = 48 MHz
1
0 = 48_24#MHz = 24 MHz
Notes:
1. Default at Power-up will be determined by the logic levels present at the bi-directional FS pins, FS3 powers up in a 0 state.
2. @Pup = Power-Up Default.
3. When in test mode, the ratio of TCLK output depends on FS3 to FS0 bit selection. Test mode is enabled when Byte0 bit2 = 1, bit1 = 0, Byte2
bit6 = 0, bit5 = 0, Byte4 bit7 = 0, bit6 = 0, bit5 = 0, Byte5 bit6 = 0, and bit5 = 0.
Byte 1: CPU, 48M Register (1 = Enable, 0 = Stopped)
Byte 2: PCI Clock Register (1=Enable, 0=Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
27
11*
1*
48*
-
27*
43
Pin Description
48_24#MHz
FS0
FS1
FS2
FS3
MODE
CPU1
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
11
-
Pin Description
PCI_F
Reserved
Reserved
PCI5
PCI4
PCI3
PCI2
PCI1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
17
16
15
13
12
44
CPU0
* This pin selection is latched at power up
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07037 Rev. **
5/02/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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