PRELIMINARY
C9641
133 MHz Clock Generator for ALI 1641 Chipset Systems
Product Features
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Supports ALI 1641 chipsets
2 CPUs at 2.5V, up to 146.2 MHz
2 -AGP Clocks at 3.3V
13 SDRAM's at 3.3V, up to 146.2 MHz
6 - PCI's Clocks at 3.3V,
1 IOAPIC at 2.5V at 14.318 MHz
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1 - 48 MHz or 24 MHz programmable via SMBus
2 REF at 3.3V, 14.318 MHz
Power management capability
SMBus programming interface
CYPRESS Spread Spectrum for EMI control
CPU to PCI offset 1.0nS to 4.0 nS (CPU early)
Available in 48 SSOP and TSSOP package
Frequency Table
48_24# MHz
SMBus Byte 0
Bit 0
0
1
24M
48M
24M
48M
24M
48M
24M
48M
24M
48M
24M
48M
24M
48M
24M
48M
FS2
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
CPU
66.82
100.23
66.82
133.64
66.82
100.23
100.23
133.64
SDRAM
100.23
100.23
66.82
100.23
133.64
133.64
66.82
133.64
AGP
66.8
66.8
66.8
66.8
66.8
66.8
66.8
66.8
PCI
33.40
33.40
33.40
33.40
33.40
33.34
33.40
33.40
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
Block Diagram
Pin Configuration
MODE
/2
48_24 MHz
REF(1:0)
FS(1,2)
PLL2
XIN
XOUT
OSC
PLL1
Spread
Spectrum
CPU
Divider
Stop
CPU(1:0)
SDRAM
Divider
SDATA
SCLK
FS(2:0)
PWR_DN#
PCI_STP#
CPU_STP#
AGP_STP#
MODE
IOAPIC
Divider
SDRAM(12:0)
Control
Logic
Stop
IOAPIC
PCI
Divider
Stop
PCI(1:5)
PCI_F
Config.
Reg.
AGP
Divider
FS0
Stop
AGP(1:0)
FS1/REF1
VDDR
XIN
XOUT
VSS
VSS
AGP0
AGP1
VDDA
VDDP
FS0/PCI_F
PCI1
PCI2
GND
PCI3
PCI4
PCI5
VDDS
CPU_STP#/SDRAM12
PCI_STP#/SDRAM11
PWR_DN#/SDRAM10
AGP_STP#/SDRAM9
VSS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
FS2/REF0
VDDI
IOAPIC
VDDC
CPU0
CPU1
VSS
VSS
SDRAM0
SDRAM1
SDRAM2
VDDS
SDRAM3
SDRAM4
SDRAM5
VSS
SDRAM6
SDRAM7
SDRAM8
VDDS
VSS48
48_24#MHZ/MODE
VDD48
SDATA
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07037 Rev. **
5/02/2001
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