PRELIMINARY
C9641
133 MHz Clock Generator for ALI 1641 Chipset Systems
PWR_DN# Timing Diagram
The power down selection is used to put the part into a low power state without turning off control power to the part.
PWR-DN# is an asynchronous active low input. This signal needs to be synchronized to affected system functions
powering down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PWR_DN# is active low, all clocks are driven
to a low value and held there prior to turning off the VCOs and crystal oscillator. The power up latency is less than 3 mS.
The power down latency conforms to the sequence requirements shown below. PCI_STP#, AGP_STP#, and
CPU_STP# are considered to be don’t cares during the power down operations. The REF and 48_24#MHz clocks are
expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding
the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PWR_DN#
CPU
SDRAM
PCI
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPU clock (defined as inside the device).
2. As shown, the outputs Stop Low on the next falling edge after PWR_DN# goes low.
3. PWR_DN# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the
device.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133 MHz operation. Similar operation will occur when the CPU clock is operating at
100 MHz.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07037 Rev. **
5/02/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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