PRELIMINARY
C9641
133 MHz Clock Generator for ALI 1641 Chipset Systems
2-Wire SMBus Control Interface
The 2-wire control interface implements a read/write slave only interface according to SMBus specification. (see fig6)
The device can be read back by using standard SMBus command bytes. Sub-addressing is not supported, thus all
preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock
output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an “acknowledge” is generated. The first byte of a
transfer cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode. R/W# = 0 in write
mode.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the “acknowledge” (low) signal
on the SDATA wire following reception of each byte. If the device should be read then an address D3 must be sent.
Data is transferred MSB first at a max rate of 100kbits/S.
The device will not respond to any other control interface conditions, and previously set control registers are retained.
Serial Control Registers
NOTE: The Pin # column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte , two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
Byte2,…) will be valid and acknowledged.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07037 Rev. **
5/02/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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