C9577
Low EMI Clock Generator/Buffers for Pentium® II Systems
Preliminary
POWER ON BIDIRECTIONAL PINS
Power up condition:
Pins 1, and 2 are Power up bi-directional pins and are used for selecting different functions in this device (see Pin description, Page
2). During power-up of the device, these pins are in input mode (see Fig 3, below), therefore; they are considered input select pins
internal to the IC. After a settling time, the Selection data is latch into internal control registers and these pins become toggling clock
outputs.
VDD rail
Power supply ramp
REF1 / SIO
REF2 / SDWN#
Hi-Z inputs
Toggle clock outputs
Select data is latched into register then pin becomes clock output signal
Fig.3
Vdd
Strapping resistor options:
The power up bidirectional pins have a large value pull-
up each (250KΩ), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
5mS settling time), then it is recommended to use an
external Pull-up (Rup) in order to insure a high
Rup
50K
IMI C9577
Rd
Load
Bidirectional
selection. In this case, the designer may choose one of
two configurations, see FIG.4A and Fig. 4B.
JP1
JUMPER
Fig4A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
Fig.4A
Rdn
5K
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in
Fig.4A. Please note the selection resistors (Rup and
Rdn) are placed before the Damping resistor (Rd) close
to the pin.
JP2
Vdd
3 Way Jumper
Fig4B represent a single resistor 10KΩ connected to a
3-way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
Rsel
10K
IMI C9577
Rd
Load
Bidirectional
Fig.4B
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Rev 1.5
4/22/1999
Page 4 of 10
CYPRESS [ CYPRESS ]
