C9577
Low EMI Clock Generator/Buffers for Pentium® II Systems
Preliminary
PIN DESCRIPTION
PIN No.
Pin Name
SI0
PWR
VDD
I/O
I
TYPE
Description
1
2
This is a bi-directional pin (see app. note, p.4). At power up, it is an input select pin,
SI0 for Selecting the frequency at pin23. When the power reaches the rail, the data is
latched into the control registers, and this pin becomes
O
I
A buffer output of the reference signal at Xin (typically a crystal).
This is a bi-directional pin (see app. note, p.4). At power up, it is an input select pin,
SDWN# for Selecting the center or down spread spectrum. When the power reaches
the rail, the data is latched into the control registers, and this pin becomes
A buffer output of the reference signal at Xin (typically a crystal).
Reference oscillator input pin. Requires either an external parallel resonant crystal
(nominally 14.318 MHz) or externally generated reference signal
Reference oscillator output pin. Drives an external parallel resonant crystal. When an
externally generated reference signal is used at Xin, this pin remains unconnected.
PCI clock outputs. They are Synchronous to the CPU clocks. See table 1 on page 1
for frequency and PCI to CPU ratio.
REF1
SDWN#
VDD
VDD
O
I
REF2
Xin
4
5
OSC1
OSC1
VDD
VDD
O
O
Xout
7,8,10,11,13,
14,16,17
PCI(_F,1:7)
22
23
VDD
VDD
O
O
a 48MHz USB clock output
This output clock frequency is selected by Strapping SIO on pin 1 as follows:
If SIO = 1, then this pin is a 48MHz USB clock
48M
24M / 48M
If SIO = 0, then this pin is a 24 MHz SIO clock.
25,26,27
I
PU
Input Select Lines for frequency selection. They have internal Pull-ups. See table1,
p.1.
S2,S1,S0
28
29,30,31
VDD
VDD
I
I
PU
PU
Input Line for enabling Spread Spectrum function When asserted Low.
These pins are for power management, and are typically controlled by the chipset
South bridge. They have internal Pull-ups, and are active LOW. (see page 3)
When CPU_stp# = 0, then CPU (1:4) are stopped in a low state synchronously.
When PCI_stp# = 0, then PCI (1:7) are stopped in a low state synchronously.
When PWR_dwn# = 0, then all clocks are stopped as well as internal circuitry.
Host (CPU) Clock outputs. See Table 1,p.1 for frequency selection.
Buffered output clock of reference oscillator at Xin. (typically a crystal at 14.31818MHz)
REF buffer output of the reference clock at Xin. (typically a crystal at 14.31818MHz)
Common Ground pins.
SSON#
PWR_dwn#
CPU_stp#
PCI_stp#
35,36,39,40
44,45
47
3,6,12,18,20,
24,32,38,43
9,15,19,21,
33,48
VDDC
VDDI
VDD
-
O
O
O
P
CPU(1:4)
IOAPIC(1:2)
REF3
VSS
-
P
3.3V power supply pins.
VDD
37,41
46
42
-
-
P
P
I
2.5V power supply pin for CPU (1:4) clocks.
2.5V power supply pin for IOAPIC (1:2) clocks.
Spread mode bandwidth control. Selects width of SSCG modulation. See table on page
5 and application data on Pin 4.
VDDC
VDDI
SMBW
VDD
PU
Table 2
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductances of the traces.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
Rev 1.5
4/22/1999
Page 2 of 10
CYPRESS [ CYPRESS ]
