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C9577AYB 参数 Datasheet PDF下载

C9577AYB图片预览
型号: C9577AYB
PDF下载: 下载PDF文件 查看货源
内容描述: [Processor Specific Clock Generator, 133.3MHz, CMOS, PDSO48, SSOP-48]
分类和应用: 时钟光电二极管外围集成电路晶体
文件页数/大小: 10 页 / 154 K
品牌: CYPRESS [ CYPRESS ]
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C9577  
Low EMI Clock Generator/Buffers for Pentium® II Systems  
Preliminary  
POWER MANAGEMENT FUNCTIONS  
Power management function is controlled at pins 29, 30, and 31 inputs PD# (PWR_DWN#), CS# (CPU_STOP#), and PS#  
(PCI_STOP#) respectively. These inputs have internal pull ups, and are active LOW. Therefore, if these pins are floating, they will  
default to a high state and do not effect the device. Typically these inputs are controlled by the South Bridge chipset.  
The clocks may be disabled according to the following tables 3 and 4 in order to reduce power consumption. All clocks are  
stopped in the low state, see fig.2. All clocks maintain a valid high period on transitions from running to stopped. The CPU and PCI  
clocks transition between running and stopped by waiting for one positive edge on PCI_F followed by a negative edge of their own  
clock. PCI_F is the clock that times the power management function in the South Bridge, therefore it does not stop until PD# = 0.  
CS#  
PS#  
PD#  
CPU(1:4)  
PCI(1:7)  
OTHER CLKs  
XTAL & VCOs  
x
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
LOW  
LOW  
LOW  
LOW  
LOW  
OFF  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
LOW  
LOW  
LOW  
RUNNING  
RUNNING  
LOW  
LOW  
RUNNING  
RUNNING  
RUNNING  
RUNNING  
LOW  
RUNNING  
RUNNING  
Table 3  
NOTE1: all clocks can be individually enabled / stopped via the I2C interface. In this case all clocks are stopped asynchronously in the low state.  
Power Management Timing Table  
Signal  
Signal State  
1 (disabled)  
Latency  
CS#  
1 rising edge of CPU_F  
1 rising edge of CPU_F  
1 rising edge of PCI_F  
1 rising edge of PCI_F  
2 mS  
0 (enabled)  
1 (disabled)  
0 (enabled)  
1 (disabled)  
0 (enabled)  
PS#  
PD#  
1 rising edge of PCI_F  
Table 4  
POWER MANAGEMENT TIMING  
PC I_F  
PS#  
wait c y c le  
s tops on nex t f alling edge  
PC I(1:7)  
C S#  
wait c y c le  
s tops on nex t f alling edge  
C PU (1:4)  
Fig. 2  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571  
Rev 1.5  
4/22/1999  
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