+/+…when timing is critical
C9530
PCIX I/O System Clock Generator With EMI Control Features
Preliminary
Transmit
ACK
ACK
ACK
ACK
ACK
Receive
1
COMMAND BYTE
(Don't Care)
BYTE COUNT
(Don't Care)
BYTE 0
(Valid)
BYTE N
(Valid)
1
0
1
0
0
1
0
SDATA
MSB
LSB
8
8
8
8
SCLK
START CONDITION
STOP CONDITION
Fig.5a (WRITE)
Transmit
ACK BYTE COUNT
BYTE 0
(Valid)
BYTE1
(Valid)
BYTE N
(Valid)
Receiv
SDATA
ACK
ACK
ACK
ACK
1
1
0
1
0
1
0
1
(Valid)
MSB
LSB
8
Fig.5b (READ)
Fig.5
8
8
8
SCLK
START CONDITION
STOP CONDITION
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown initially only after true power up condition occurs.
Following the acknowledge of the Address Byte , two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
3)
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
Byte 0: Function Select Register
@Pup
Pin#
Description
Bit
7
6
5
4
3
2
1
0
1
0
1
1
1
1
1
1
-
27
-
42
43
7
Test Mode Enable. 1=normal operation, 0 = Test mode
Spread Spectrum modulation control bit (effective only when Bit 0 of this register is set to a 0) 0=OFF, 1 = ON
SSCG Spread width select. 1=0.5%, 0=1.0%
SB1 Bank B MSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
SB0 Bank B LSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
SA1 Bank A MSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
SA0 Bank A LSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
Hardware/I2C frequency control. 1=Hardware (pins 6, 7, 42, 43, and 27), 0=I2C Byte 0 bits 1-4 and 6
6
-
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571
http://www.imicorp.com
Rev. 1.2
3/12/2000
Page 5 of 13
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