+/+…when timing is critical
C9530
PCIX I/O System Clock Generator With EMI Control Features
Preliminary
Pin Description
Pin No.
Pin Name
PWR
I/O
Description
3
XIN
XOUT
REF
VDDA
I
Crystal Buffer input pin. Connects to a crystal, or an external clock
source. Serves as input clock TCLK, in Test mode.
Crystal Buffer output pin. Connects to a crystal only. When a Can
Oscillator is used or in Test mode, this pin is kept unconnected.
Buffered inverted outputs of the signal applied at Xin, typically 33.33
MHz
Output Enable for clock bank A. Causes the CLKA (0:4) output
clocks to be in a Tri-state condition when driven to a logic low level.
Output Enable for clock bank B. Causes the CLKB (0:4) output
clocks to be in a Tri-state condition when driven to a logic low level.
When this output signal is a logic low level, it indicates that the
output clocks of the A bank are locked to the input reference clock.
When this output signal is at a logic low level, it indicates that the
output clocks of the B bank are locked to the input reference clock.
Clock Bank A selection bits. These control the clock frequency that
will be present on the outputs of the A bank of buffers. See table on
page one for frequency codes and selection values.
4
1
VDDA
VDD
VDD
VDD
VDD
VDD
VDD
O
O
I
24*
25*
18
OEA
OEB
I
AGOOD#
BGOOD#
SA(0,1)
O
O
I
31
6*, 7*
43*, 42*
SB(0,1)
VDD
I
Clock Bank B selection bits. These control the clock frequency that
will be present on the outputs of the B bank of buffers. See table on
page one for frequency codes and selection values.
20*, 21*, 22*
27*
IA(0:2)
SSCG#
VDD
VDD
I
I
I2C address selection input pins. See I2C Address table.
Enables Spread Spectrum clock modulation when at a logic low
level, see pg. 3.
48
47
11, 14
SDATA
SCLK
VDDA
VDDB
VDD
VDD
VDD
-
-
-
-
I/O
I
Data for the internal I2C circuitry. See pg 4.
Clock for the internal I2C circuitry. See pg. 4
PWR 3.3V common power supply pin for Bank A PCI clocks (CLKA (0:4).
PWR 3.3V common power supply pin for Bank B PCI clocks (CLKB (0:4).
PWR Power supply for internal Core logic.
PWR Power for internal analog circuitry. This supply should have a
separately decoupled current source from VDD.
38, 35
2, 44, 46
23, 29, 30
AVDD
9, 10, 12,
15, 16
40, 39, 37,
34, 33
5, 8, 13, 17,
19, 26, 28,
32, 36, 41,
45
CLKA
(0:4)
CLKB
(0:4)
VDDA
VDDB
-
O
A bank of Five 33.3, 66.6, 100.0 or 133.3 MHz output clocks (1x, 2x,
3x and 4x Xin clock).
A bank of Five 33.3, 66.6, 100.0 or 133.3 MHz output clocks (1x, 2x,
3x, and 4x Xin clock).
O
VSS
PWR Ground pins for the device
Notes: Pin numbers ending with a * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no
external circuitry is connected to them.
A bypass capacitor (0.1 µF) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins, their high
frequency filtering characteristic will be canceled by the lead inductance of the trace. PWR = Power connection, I = Input, O = Output and I/O = both
input and output functionality of the pin(s).
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571
http://www.imicorp.com
Rev. 1.2
3/12/2000
Page 2 of 13
CYPRESS [ CYPRESS ]
