+/+…when timing is critical
C9530
PCIX I/O System Clock Generator With EMI Control Features
Preliminary
Output Clock Tri-state Control
All of the clocks in Bank A (CLKA(0:4)) and bank B (CLKB(0:4)) may be placed in a tri-state condition by bringing their
relevant OE pins (OEA and OEB) to a logic low state. This transition to and from a tristate and active condition is a
totally asynchronous event and clock glitching may occur during the transitioning states. This function is intended as a
board level testing feature. When output clocks are being enabled and disabled in active environments the I2C control
register bits are the preferred mechanism to control these signals in an orderly and predictable manner.
Both output enable pins contain internal pull-up resistors that will insure that a logic 1 (high) is maintained and sensed
by the device if no external circuitry is connected to these pins.
Absolute Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Maximum Power Supply:
Storage Temperature:
Operating Temperature:
Maximum ESD protection
5.5
-65ºC to + 150ºC
0ºC to +70ºC
2000V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD)
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571
http://www.imicorp.com
Rev. 1.2
3/12/2000
Page 7 of 13
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