+/+…when timing is critical
C9530
PCIX I/O System Clock Generator With EMI Control Features
Preliminary
AC Parameters
Symbol
Parameter
Output Frequency
100 MHz 66 MHz
Min Max Min Max Min Max Min Max
Units Notes
133 MHz
33 MHz
Tcyc
CLKA(0:4) CLKB(0:4)
period
7.0
8.0
9.5 10.5 14.5 15.5 25.5 30.5
nS
1, 2, 4
THIGH
TLOW
CLKA(0:4) CLKB(0:4) period
CLKA(0:4) CLKB(0:4) low
time
3
3
-
-
6
6
-
-
8
8
-
-
11
11
-
-
nS
nS
2,6
2, 7
Tr / Tf
TSKEW
TCCJ
CLKA(0:4) a, CLKB(0:4)rise
and fall times
(Any CLK ) to (Any CLK)
Skew time
CLK(A:B)(0:4) Cycle to
Cycle Jitter
0.50 1.33 0.50 1.33 0.50 1.33 0.50 1.33
nS
pS
pS
2, 3
-
250
4.0
-
250
-
250
4.0
-
250
4.0
2, 4,
5. 9
2, 4,
5, 10
250 or 175
(see note 10)
Tr / Tf
TCCJ
REFOUT rise and fall times
REFOUT Cycle to Cycle
Jitter
1.0
1.0
4.0
1.0
1.0
nS
pS
2, 3
2, 4
750
tpZL, tpZH OE to clock enable delay (all
-
-
-
10.0
10.0
3
-
-
-
10.0
10.0
3
-
10.0
10.0
3
-
-
-
10.0
10.0
3
nS
nS
outputs)
tpLZ, tpHZ OE to clock disable delay (all
outputs)
-
tstable
All clock Stabilization from
power-up
-
mS
8
Note 1: This parameter is measured as an average over 1uS duration, with an input frequency of 33.333 MHz
Note 2: All outputs loaded as per table 1 below.
Note 3: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V (see Fig.6A and Fig.6B)
Note 4: Probes are placed on the pins, and measurements are acquired at 1.5V. (See Figs.6A & 6B)
Note 5: This measurement is applicable with Spread ON or OFF.
Note 6: Probes are placed on the pins, and measurements are acquired at 2.4Vs, (see Figs. 6A & 6B)
Note 7: Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 8: The time specified is measured from when all VDD’s reach their respective supply rail (3.3V) till the frequency output is stable and operating
within the specifications
Note 9: Applicable only to clocks within the same bank
Note10: The cycle to cycle jitter of the device is dependent on 2 factors. They are the jitter component of the input reference clock and whether the 2
output clock banks are operating at the same frequency, When the frequency of the output banks is the same, output jitter is guaranteed to
not be more than 175pSec. When the output clocks of each bank differ in frequency, the device is guaranteed to be no more than 250
pSec.
Output Name
Max Load (in pF)
REF
CLK(A:B)(0:4)
20
30
Table 1
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571
http://www.imicorp.com
Rev. 1.2
3/12/2000
Page 9 of 13
CYPRESS [ CYPRESS ]
