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Preliminary
Product Features
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…when timing is critical
C9530
PCIX I/O System Clock Generator With EMI Control Features
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Dedicated clock buffer power pins for reduced
noise, crosstalk and jitter
Buffer XIN Reference clock output
Input clock frequency 33.3 MHz
Reference may be a clock or a crystal
Output frequencies of 33.3, 66.6, 100 and 133.3
MHz selectable (PCIX requirements)
Output grouped in two banks of 5 clocks each.
2
I C clock control interface for individual clock
disabling, SSCG control and individual bank
frequency selection
Output clock duty cycle is 50% (± 5%)
<250 pS skew between output clocks within a
bank
Output jitter <250 pSec. (175pSec with all
outputs at the same frequency)
Spread Spectrum feature for reduced EMI
OE pins for separate output bank enable control
and testability
48 Pin SSOP and TSSOP package
Test Mode Logic Table
INPUT PINS
OEA
OEB
HIGH
HIGH
HIGH
HIGH
LOW
SA1
SB1
LOW
LOW
HIGH
HIGH
X
SA0
SB0
LOW
HIGH
LOW
HIGH
X
OUTPUT PINS
CLKA(0:4)
CLKB(0:4)
XIN
2 X XIN
3 X XIN
4 X XIN
Tri-State
REF
XIN
XIN
XIN
XIN
Tri-State
Note:
A and B banks have separate frequency select
and output enable controls. XIN is the frequency of
the clock on the device’s XIN pin. OEA or OEB will
tristate REF.
Pin Configuration
REF
VDD
XIN
XOUT
VSS
SA0
SA1
VSS
CLKA0
CLKA1
VDDA
CLKA2
VSS
VDDA
CLKA3
CLKA4
VSS
AGOOD#
VSS
IA0
IA1
IA2
AVDD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
SDATA
SCLK
VDD
VSS
VDD
SB0
SB1
VSS
CLKB0
CLKB1
VDDB
CLKB2
VSS
VDDB
CLKB3
CLKB4
VSS
BGOOD#
AVDD
AVDD
VSS
SSCG#
VSS
OEB
Block Diagram
AGOOD#
SSCG#
SSCG
Logic
/N
1
0
C9530
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
OEA
CLKB0
CLKB1
CLKB2
CLKB3
CLKB4
OEB
BGOOD#
REF
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
XIN
XOUT
0
SDATA
SCLK
IA(0:2)
SA(0,1)
SB(0,1)
/N
I
2
C
Control
Logic
1
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300, FAX: 263-6571
http://www.imicorp.com
Rev. 1.2
3/12/2000
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