ADS5231
www.ti.com
SBAS295A–JULY 2004–REVISED JANUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
ADS5231
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Differential Input Capacitance
3
pF
V
Analog Input Common-Mode Range
Differential Input Voltage Range
V
CM ± 0.05
Internal Reference
External Reference
2.02
VPP
2.02 × (VREFT – VREFB)
VPP
Voltage Overload Recovery Time(8)
Input Bandwidth
3
CLK Cycles
–3dBFS Input, 25Ω Series
300
MHz
Resistance
DIGITAL DATA INPUTS
Logic Family
VIH High-Level Input Voltage
VIL Low-Level Input Voltage
CIN Input Capacitance
DIGITAL OUTPUTS
+3V CMOS Compatible
VIN = 3.3V
VIN = 3.3V
2.2
0.6
3
V
V
pF
Data Format
Straight Offset Binary(9)
Logic Family
CMOS
Logic Coding
Straight Offset Binary or BTC
Low Output Voltage (IOL = 50µA)
High Output Voltage (IOH = 50µA)
3-State Enable Time
+0.4
V
V
+2.4
2
2
3
Clocks
Clocks
pF
3-State Disable Time
Output Capacitance
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
CONVERSION CHARACTERISTICS
Sample Rate
20
MHz
20
40
MSPS
Data Latency
6
CLK Cycles
(8) A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the
full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the
ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value
when the pulse is switched from ON (high) to OFF (low).
(9) Option for Binary Two’s Complement Output.
5
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