ADS5231
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SBAS295A–JULY 2004–REVISED JANUARY 2007
RECOMMENDED OPERATING CONDITIONS
ADS5231
MIN
TYP
MAX
UNITS
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, VDRV
REFT — External Reference Mode
REFB — External Reference Mode
REFCM = (REFT + REFB)/2 – External Reference Mode(1)
Reference = (REFT – REFB) – External Reference Mode
Analog Input Common-Mode Range(1)
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate
PLL Enabled (default)
3.0
3.0
3.3
3.3
3.6
3.6
V
V
V
V
V
V
V
1.875
0.95
2.0
2.05
1.125
1.0
V
CM ± 50mV
1.0
0.75
1.1
V
CM ± 50mV
20
2
40
30(2)
MSPS
MSPS
PLL Disabled
ADCLK Duty Cycle
PLL Enabled (default)
45
55
MSPS
Low-Level Voltage Clock Input
High-Level Voltage Clock Input
Operating Free-Air Temperature, TA
Thermal Characteristics:
0.6
V
V
2.2
–40
+85
°C
θJA
42.8
18.7
°C/W
°C/W
θJC
(1) These voltages need to be set to 1.5V ± 50mV if they are derived independent of VCM
.
(2) When the PLL is disabled, the clock duty cycle needs to be controlled well, especially at higher speeds. A 45%–55% duty cycle variation
is acceptable up to a frequency of 30MSPS. If the device needs to be operated in the PLL disabled mode beyond 30MSPS, then the
duty cycle needs to be maintained within 48%–52% duty cycle.
3
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