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ADS5231 参数 Datasheet PDF下载

ADS5231图片预览
型号: ADS5231
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道,12位,40Msps, + 3.3V模拟数字转换器 [Dual, 12-Bit, 40MSPS, +3.3V Analog-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 26 页 / 572 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ADS5231  
www.ti.com  
SBAS295AJULY 2004REVISED JANUARY 2007  
TIMING CHARACTERISTICS(1)  
Typical values at TA = +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% duty  
cycle, and total capacitive loading = 10pF, unless otherwise noted.  
PARAMETER  
MIN  
TYP  
MAX  
UNITS  
40MSPS With PLL ON  
tA Aperture Delay  
Aperture Jitter  
2.1  
1.0  
5.5  
13.5  
6
ns  
ps  
t1 Data Setup Time(2)  
t2 Data Hold Time(3)  
3.7  
ns  
11.5  
ns  
tD Data Latency  
Clocks  
ns  
tDR, tDF Data Rise/Fall Time(4)  
Data Valid (DV) Duty Cycle  
tDV Input Clock Rising to DV Fall Edge  
0.5  
2
3
30  
13.5  
40  
16  
55  
%
18.5  
ns  
30MSPS With PLL OFF  
tA Aperture Delay  
Aperture Jitter  
2.1  
1.0  
10  
19  
6
ns  
ps  
t1 Data Setup Time  
8
ns  
t2 Data Hold Time  
14  
ns  
tD Data Latency  
Clocks  
ns  
tDR, tDF Data Rise/Fall Time  
Data Valid (DV) Duty Cycle  
tDV Input Clock Rising to DV Fall Edge  
0.5  
2
3.5  
55  
21  
30  
16  
45  
19  
%
ns  
20MSPS With PLL ON  
tA Aperture Delay  
Aperture Jitter  
2.1  
1.0  
12  
25  
6
ns  
ps  
t1 Data Setup Time  
10  
20  
ns  
t2 Data Hold Time  
ns  
tD Data Latency  
Clocks  
ns  
tDR, tDF Data Rise/Fall Time  
Data Valid (DV) Duty Cycle  
tDV Input Clock Rising to DV Fall Edge  
0.5  
2
3.5  
55  
30  
30  
20  
45  
25  
%
ns  
20MSPS With PLL OFF  
tA Aperture Delay  
Aperture Jitter  
2.1  
1.0  
12  
25  
6
ns  
ps  
t1 Data Setup Time  
10  
20  
ns  
t2 Data Hold Time  
ns  
tD Data Latency  
Clocks  
ns  
tDR, tDF Data Rise/Fall Time  
Data Valid (DV) Duty Cycle  
tDV Input Clock Rising to DV Fall Edge  
0.5  
2
3.5  
55  
30  
30  
20  
45  
25  
%
ns  
2MSPS With PLL OFF  
tA Aperture Delay  
Aperture Jitter  
2.1  
1.0  
200  
250  
6
ns  
ps  
t1 Data Setup Time  
150  
200  
ns  
t2 Data Hold Time  
ns  
tD Data Latency  
Clocks  
ns  
tDR, tDF Data Rise/Fall Time  
Data Valid (DV) Duty Cycle  
tDV Input Clock Rising to DV Fall Edge  
0.5  
30  
2
3.5  
55  
45  
%
200  
225  
250  
ns  
(1) Specifications assured by design and characterization; not production tested.  
(2) Measured from data becoming valid (at a high level = 2.0V and a low level = 0.8V) to the 50% point of the falling edge of DV.  
(3) Measured from the 50% point of the falling edge of DV to the data becoming invalid.  
(4) Measured between 20% to 80% of logic levels.  
7
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