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ADS5231 参数 Datasheet PDF下载

ADS5231图片预览
型号: ADS5231
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道,12位,40Msps, + 3.3V模拟数字转换器 [Dual, 12-Bit, 40MSPS, +3.3V Analog-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 26 页 / 572 K
品牌: BURR-BROWN [ BURR-BROWN CORPORATION ]
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Burr Brown Products
from Texas Instruments
SBAS295A – JULY 2004 – REVISED JANUARY 2007
Dual, 12-Bit, 40MSPS, +3.3V
Analog-to-Digital Converter
FEATURES
Single +3.3V Supply
High SNR: 70.7dBFS at f
IN
= 5MHz
Total Power Dissipation:
Internal Reference: 321mW
External Reference: 285mW
Internal or External Reference
Low DNL:
±0.3LSB
Flexible Input Range: 1.5V
PP
to 2V
PP
TQFP-64 Package
DESCRIPTION
The ADS5231 is a dual, high-speed, high dynamic
range, 12-bit pipelined analog-to-digital converter
(ADC). This converter includes a high-bandwidth
sample-and-hold amplifier that gives excellent
spurious performance up to and beyond the Nyquist
rate. The differential nature of the sample-and-hold
amplifier and ADC circuitry minimizes even-order
harmonics and gives excellent common-mode noise
immunity.
The ADS5231 provides for setting the full-scale
range of the converter without any external reference
circuitry. The internal reference can be disabled,
allowing low-drive, external references to be used for
improved tracking in multichannel systems.
The ADS5231 provides an over-range indicator flag
to indicate an input signal that exceeds the full-scale
input range of the converter. This flag can be used to
reduce the gain of front-end gain control circuitry.
There is also an output enable pin to allow for
multiplexing and testing on a printed circuit board
(PCB).
The ADS5231 employs digital error correction
techniques to provide excellent differential linearity
for demanding imaging applications. The ADS5231 is
available in a TQFP-64 package.
AVDD
SDATA SEN SCLK SEL
VDRV
OE
A
APPLICATIONS
Communications IF Processing
Communications Base Stations
Test Equipment
Medical Imaging
Video Digitizing
CCD Digitizing
ADS5231
Serial
Interface
DISABLE_PLL
IN
A
V
IN
IN
A
S/H
12-Bit
Pipelined
ADC
Error
Correction
Logic
3-State
Output
D11A
D0A
·
·
·
OVR
A
DV
A
INT/EXT
CM
REF
T
REF
B
IN
B
V
IN
S/H
IN
B
12-Bit
Pipelined
ADC
Error
Correction
Logic
DV
B
D11B
D0B
Internal
Reference
Timing/Duty Cycle
Adjust (PLL)
CLK
3-State
Output
·
·
·
OVR
B
STPD
OE
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated