S2044/S2045
GLM COMPLIANT SERIAL INTERFACE CIRCUITS
generated bit clock which is 10 times the REFCLK
input frequency. The state of the serial outputs is
controlled by the output enable pins, OE0 and OE1.
D10 is transmitted first in 10-bit mode. D0 is transmit-
ted first in 20-bit mode. Table 2 shows the mapping
of the parallel data to the 8B/10B codes.
S2044 TRANSMITTER FUNCTIONAL
DESCRIPTION
The S2044 transmitter accepts parallel input data
and serializes it for transmission over fiber optic or
coaxial cable media. The chip is fully compatible with
the ANSI X3T11 Fibre Channel standard, and sup-
ports the Fibre Channel standard's data rates of 1062,
531 and 266 Mbit/sec.
10-Bit/20-Bit Mode
The S2044 operates with either 10-bit or 20-bit parallel
data inputs. Word width is selectable via the DWS pin. In
10-bit mode, D10–D19 are used and D0-D9 are ignored.
The parallel input data word can be either 10 bits or
20 bits wide, depending upon DWS pin selection. A
block diagram showing the basic chip function is
shown in Figure 3.
Reference Clock Input
The reference clock input (REFCLK) must be sup-
plied with a PECL single-ended AC coupled crystal
clock source with 100 PPM tolerance to assure that
the transmitted data meets the Fibre Channel fre-
quency limits. The internal serial clock is frequency
locked to the reference clock. The word rate clock
(TCLK, TCLKN) output frequency is determined by
the selected operating speed and word width. Refer
to Table 1 for TCLK/TCLKN clock frequencies.
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit or 20-
bit wide data from the input latch and converts it to a
serial data stream. Parallel data is latched into the
transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
Table 2. Data Mapping to 8b/10b Alphabetic Representation
First Data Byte
Second Data Byte
TX[00:19] or
0
a
1
b
2
c
3
d
4
e
5
i
6
f
7
g
8
h
9
j
10 11 12 13 14 15 16 17 18 19
RX[00:19]
8b/10b alphabetic
representation
a
b
c
d
e
i
f
g
h
j
First bit transmitted in 20-bit mode
First bit transmitted in 10-bit mode
Figure 4. S2045 Functional Block Diagram
REFSEL
RATESEL
[-LCK_REF] LOCK_REF
LOCKDETN
[TBC] REFCLK
SHIFT
REGISTER
D
RX
RY
PLL CLOCK
RECOVERY
2:1
RLX
RLY
20
BITCLK
D
Q
D(0:19)
[RX(00:19)]
[EWRAP] LPEN
CONTROL
[EN_CDET] SYNCEN
LOGIC
SYNC [COM_DET]
RCLK [RBC1]
SYNC
DETECT
LOGIC
DWS
[LUNUSE]
[FAULT]
[PARID1]
RCLKN
[RBC0]
[ ] GLM Interface PIns
[STROBE ID]
3
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
