GLM COMPLIANT SERIAL INTERFACE CIRCUITS
S2044/S2045
S2044 Pin Assignment and Descriptions (Continued)
Pin Name Level I/O
Pin #
Description
OE0
Static
TTL
I
I
I
I
2
Active low output-enable control for TX/TY outputs. TX/TY will
go to the logic low state when disabled.
OE1
1
Active low output-enable control for TLX/TLY outputs. TLX/TLY
will go to the logic low state when disabled.
TTL
REFSEL
RATESEL
Static
TTL
18
15
Multilevel input used to select the reference clock frequency.
(See Table 1.)
Static
TTL
Multilevel input used to select the operating speed of the
transmitter. (See Table 1.)
ECLVCC
TTLGND
TTLVCC
+3.3V
GND
–
–
–
21, 39
Core +3.3V
14
17
TTL Ground
+3.3V/
+5V
TTL Power Supply (+5V if TTL)
ECLIOVCC
ECLIOVEE
AVCC
+3.3V
+3.3V
+3.3V
GND
–
–
–
–
–
3, 10
6, 7
PECL I/O Power Supply
PECL I/O Power Supply
Analog Power Supply
Analog Ground
27, 32
26, 33
AVEE
ECLVEE
GND
13, 40,
51, 52
Core Ground
TX_SI
Multi-
level
I
34
Multilevel signal that determines where the data which is
presented to the link comes from and whether the ±SO signals
are enabled. When this input is low, the TX/TY outputs transmit
the serialized data from the parallel transmit data lines. When
this input is high, the TX/TY outputs transmit the data from the
±SI inputs.
+SI
–SI
Diff.
PECL
I
45
46
These inputs are a serial data stream (1.0625 Gb/s, 531.25
Mb/s, 265.625) which shall control the link modulation (TX/TY) if
the TX_SI input is high.
8
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
