S2044/S2045
GLM COMPLIANT SERIAL INTERFACE CIRCUITS
S2045 Pin Assignment and Descriptions
Pin Name
Level I/O
Pin # Description
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
TTL
O
45
43
42
40
38
37
35
34
32
31
29
28
25
24
22
21
18
17
15
14
Outputs parallel data. The width of the parallel data bus is
selected by the state of the DWS pin. Parallel data on this bus is
clocked out on the falling edge of RCLK. In 20-bit mode, D0 is
the first bit received. In 10-bit mode, D10-D19 are used and D0-
D9 are driven to the high state. In 10-bit mode, D10 is the first
bit received.
D8
D7
D6
D5
D4
D3
D2
D1
D0
LOCKDETN
TTL
TTL
O
52
When LOW, LOCKDETN indicates that the PLL is locked to the
incoming data stream. When HIGH, it provides a system flag
indicating that the PLL is locked to the local reference clock.
LPEN
DWS
I
I
8
4
When HIGH, LPEN selects the loopback differential serial input
pins. When LOW, LPEN selects RX and RY (normal operation).
Static
TTL
The level on this pin selects the parallel data bus width. When
LOW, a 20-bit parallel bus width is selected, and D(0-19) are
active. When HIGH, a 10-bit parallel data bus is selected, D(10-
19) are active and D(0-9) will go HIGH. (See Table 4.) A rising
edge will reset the internal counters (used for test).
RCLK
RCLKN
Diff.
TTL
O
49
48
The falling edge of RCLK outputs a new word on the data bus.
After a sync word is detected, the period of the current RCLK
and RCLKN is stretched to align with the word boundary. (See
Table 4 for frequency.)
REFCLK
SYNC
PECL
TTL
I
2
(Externally capacitively coupled.) A free-running crystal-
controlled reference clock for the PLL clock multiplier. The
frequency of REFCLK is set by the REFSEL pin. (See Table 4.)
O
51
Upon detection of a valid sync symbol, this output goes high for
one RCLK period. When sync is active, the sync symbol shall be
present on the parallel data bus bits D0-D9 in 20-bit mode or
D10-D19 in 10-bit mode.
RLX
RLY
Diff.
I
I
11
12
(Externally capacitively coupled.) The serial loopback data
inputs. RLX is the positive input, and RLY is the negative input.
PECL
RX
RY
Diff.
PECL
9
10
(Externally capacitively coupled.) The received serial data
inputs. RX is the positive input, and RY is the negative input.
9
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
