GLM COMPLIANT SERIAL INTERFACE CIRCUITS
S2044/S2045
OVERVIEW
Loopback
Local loopback is supported by the chipset, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
The S2044 transmitter and S2045 receiver provide
serialization and deserialization functions for block-
encoded data to implement a Fibre Channel interface.
Operation of the S2044/S2045 chips is straightfor-
ward, as depicted in Figure 2. The sequence of
operations is as follows:
Figure 2. Fibre Channel Interface Diagram
Transmitter
1. 10/20-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Parallel
Data Out
Parallel
Data In
Serial
Data
TCLK
RCLK
S2044
Transmitter
S2045
Receiver
Receiver
Sync
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
Loopback
Loopback
RefClk
RefClk
4. 10/20-bit parallel output
Lock
Detect
The 10/20-bit parallel data handled by the S2044 and
S2045 devices should be from a DC-balanced en-
coding scheme, such as the 8B/10B transmission
code, in which information to be transmitted is en-
coded 8 bits at a time into 10-bit transmission characters1.
Table 1. Transmitter Operating Modes
Reference
Clock
Word
TCLK/TCLKN
Width Frequency Frequency
Data Rate
(Mbits/sec)
RATESEL DWS REFSEL
(Bits)
(MHz)
(MHz)
Internal clocking and control functions are transparent to
the user. Details of data timing can be seen in Figure 5.
0
0
1
0
1
0
10
20
106.25
53.125
53.125
53.125
1062.5
1062.5
A lock detect feature is provided on the receiver, which
indicates that the PLL is locked (synchronized) to the
data stream.
1
1
1
0
1
0
10
20
53.125
26.5625
53.125
26.5625
531.25
531.25
Open
1
1
10
26.5625
26.5625
265.625
Figure 3. S2044 Functional Block Diagram
[TX_SI]
[ ] OE0
OE1
10
10
20
2:1
D
Q
[Tx(00:19)] D(19..0)
10
0
TX
TY
MUX
1
[+ SI]
[– SI]
DIVIDE-BY-2
SHIFT
REGISTER
TEST
DWS
TLX [+SO]
CONTROL
LOGIC
TLX [-SO]
REFSEL
TCLK
DIVIDE-BY-2
RATESEL
PLL CLOCK
MULTIPLIER
= F X 10/20
TCLKN
[TBC] REFCLK
F
0
1
[ ] = GLM Interface Pins
1. A.X. Widmer and P.A. Franaszek, “A Byte-Oriented DC Balanced (0,4) 8B/10B Transmission Code,” IBM Research Report RC 9391, May 1982.
2
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
