VT82C686B
Port 61 - Misc Functions & Speaker Control................. RW
Register Descriptions
........................................always reads 0
7
6
Reserved
.................................................RO
IOCHCK# Active
Legacy I/O Ports
This bit is set when the ISA bus IOCHCK# signal is
asserted. Once set, this bit may be cleared by setting
bit-3 of this register. Bit-3 should be cleared to
enable recording of the next IOCHCK#. IOCHCK#
generates NMI to the CPU if NMI is enabled.
This group of registers includes the DMA Controllers,
Interrupt Controllers, and Timer/Counters as well as a number
of miscellaneous ports originally implemented using discrete
logic on original PC/AT motherboards. All of the registers
listed are integrated on-chip. These registers are implemented
in a precise manner for backwards compatibility with previous
generations of PC hardware. These registers are listed for
information purposes only. Detailed descriptions of the
actions and programming of these registers are included in
numerous industry publications (duplication of that
information here is beyond the scope of this document). All of
these registers reside in I/O space.
......................................RO
Timer/Counter 2 Output
This bit reflects the output of Timer/Counter 2
without any synchronization.
5
4
3
...................................................RO
Refresh Detected
This bit toggles on every rising edge of the ISA bus
REFRESH# signal.
...............................................RW
IOCHCK# Disable
0
1
Enable IOCHCK# assertions ................. default
Force IOCHCK# inactive and clear any
“IOCHCK# Active” condition in bit-6
........................................RW, default=0
2
1
Reserved
....................................................RW
Speaker Enable
0
1
Disable................................................... default
Enable Timer/Ctr 2 output to drive SPKR pin
.....................................RW
0
Timer/Counter 2 Enable
0
1
Disable................................................... default
Enable Timer/Counter 2
Port 92h - System Control................................................ RW
7-6 Hard Disk Activity LED Status
0
Off
.................................................... default
1-3 On
........................................always reads 0
5-4 Reserved
..default=0
Power-On Password Bytes Inaccessable
3
2
1
........................................always reads 0
Reserved
A20 Address Line Enable
0
A20 disable / forced 0 (real mode) ........ default
1
A20 address line enable
0
High Speed Reset
0
Normal
1
Briefly pulse system reset to switch from
protected mode to real mode
Revision 1.71 June 9, 2000
-39-
Register Descriptions - Legacy I/O Ports
ETC [ ETC ]
