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VT82C686B 参数 Datasheet PDF下载

VT82C686B图片预览
型号: VT82C686B
PDF下载: 下载PDF文件 查看货源
内容描述: PCI SUPER -I / O集成外设控制器 [PCI Super-I/O Integrated Peripheral Controller]
分类和应用: 控制器PC
文件页数/大小: 128 页 / 1074 K
品牌: ETC [ ETC ]
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VT82C686B  
Internal Keyboard Controller  
Signal Name  
Pin #  
I/O  
Signal Description  
(Internal mouse controller enabled by Rx5A[1])  
MultiFunction Pin  
/ IRQ1  
D5  
IO / I  
IO / I  
IO / I  
IO / I  
MSCK  
MSDT  
KBCK  
KBDT  
Rx5A[1]=1  
From internal mouse controller.  
Mouse Clock.  
Rx5A[1]=0  
. Interrupt input 1.  
Interrupt Request 1  
/ IRQ12  
C5  
E5  
A5  
(Internal mouse controller enabled by Rx5A[1])  
MultiFunction Pin  
Rx5A[1]=1  
Rx5A[1]=0  
From internal mouse controller.  
Mouse Data.  
. Interrupt input 12.  
Interrupt Request 12  
/ A20GATE  
/ KBRC  
(Internal keyboard controller enabled by Rx5A[0])  
MultiFunction Pin  
Rx5A[0]=1  
From internal keyboard controller  
Keyboard Clock.  
Rx5A[0]=0  
Input from external keyboard controller.  
Gate A20.  
(Internal keyboard controller enabled by Rx5A[0])  
MultiFunction Pin  
Rx5A[0]=1  
Rx5A[0]=0  
From internal keyboard controller.  
From external keyboard controller (KBC)  
Keyboard Data.  
Keyboard Reset.  
for CPURST# generation  
/ ROMCS# /  
C1  
O / O / I  
I / IO  
(Rx5A[0]=0). To external keyboard controller chip.  
Keyboard Chip Select  
KBCS#  
strap  
:
Power-Up Configuration Strap (Sampled At Reset)  
4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1  
/ SD[7-4]  
W4,  
Y4,  
V3,  
W3  
Sampled at reset on SD[7-4] and latched into  
KBIN[6-3]  
Keyboard Inputs 6-3.  
Rx5A[7-4].  
Chip Selects  
Signal Name  
/ KBCS# /  
Pin #  
I/O  
Signal Description  
C1  
O
(Rx5A[0]=1). Chip Select to the BIOS ROM.  
ROM Chip Select  
ROMCS#  
strap  
:
Power-Up Configuration Strap (Sampled At Reset)  
4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1  
/ GPO12 / XDIR  
T5  
O
(Rx76[1] = 1 and Rx8B[0] = 1). Asserted  
Programmable Chip Select 0  
PCS0#  
during I/O cycles to programmable read or write ISA I/O port ranges.  
Addressed devices drive data to the SD pins (XDIR is disabled and the X-  
Bus is not implemented). See also Rx59[3] and Rx77[2].  
/ GPO13 / SOE#  
U5  
U8  
O
O
(Rx76[3] = 1, Rx76[4] = 0, Rx77[0] = 1).  
Asserted during read or write accesses to I/O ports 62h or 66h.  
MCCS#  
MCCS#  
Microcontroller Chip Select  
/ GPI11 / GPO11  
/ GPIOD  
(Rx76[4] = 0 selects MCCS#  
Microcontroller Chip Select (Alternate Pin)  
on pin U8, Rx76[4] = 1 selects MCCS# on pin U5). Rx76[3] = 1 enables  
MCCS# output on the selected pin.  
Revision 1.71 June 9, 2000  
-21-  
Pinouts  
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