VT82C686B
3)
defined in the GBL_STS and
Generic Global Events
Power Management Events
GBL_EN registers. These registers are mainly used for
SMI:
Three types of power management events are supported:
1)
defined in the PM1a_STS
and PM1a_EN registers. These events can trigger either
SCI or SMI depending on the SCI_EN bit:
ACPI-required Fixed Events
• PCI Bus Clock Run Resume
• Primary Interrupt Occurance
• GP0 and GP1 Timer Time Out
• Secondary Event Timer Time Out
• Occurrence of Primary Events
(defined in register PACT_STS and PACT_EN)
• Legacy USB accesses (keyboard and mouse)
- Software SMI
• PWRBTN# Triggering
• RTC Alarm
• Sleep Button
• ACPI Power Management Timer Carry (always SCI)
• BIOS Release (always SCI)
2)
defined
ACPI-aware General Purpose Function Events
System and Processor Resume Events
in the GP_STS and GP_SCI_EN, and GP_SMI_EN
registers. These events can trigger either SCI or SMI
depending on the setting of individual SMI and SCI
enable bits:
Depending on the system suspend state, different features can
be enabled to resume the system. There are two classes of
resume events:
a) VCCS-based events. Event logic resides in the
VCCS plane and thus can resume the system from
any suspend state. Such events include PWRBTN#,
RI#, BATLOW#, LID, SMBus resume event, RTC
alarm, EXTSMI#, and GP1 (EXTSMI1#).
b) VCC-Based Events. Event logic resides in the VCC
plane and thus can only resume the system from the
POS state. Such events include the ACPI PM timer,
USB resume, and EXTSMIn#.
• External SMI triggering
• USB Resume
• Ring Indicator (RI#)
• Battery Low Detect (BATLOW#)
• Notebook Lid Open/Close Detect (LID)
• Thermal Detect (THRM#)
HCLK
SMI# / STPCLK#
Host CPU
CPU Bus
L2 Cache
SMIACT#
(Socket-7 Only)
GCLK
3D
Graphics
Controller
FPG, EDO, or
SDRAM
(SDR or DDR)
Memory Bus
VT82C598
(Apollo MVP3)
or
VT82C693
(Apollo ProPlus)
AGP Bus
CKE#
GCKRUN#
HCLK
GCLK
PCLK
PCKRUN#
Module ID
PCI Bus
PCLK
SUSCLK,
SUSST1#
MCLK
ISA
SMBus
VT82C686A
Super South
CPUSTP#
PCISTP#
IDE
Clock
Generator
BIOS ROM
USB
Keyboard / Mouse
GPIO and ACPI Events
Power Plane & Peripheral Control
Figure 7. System Block Diagram Using the VT82C686B Super South Bridge
Revision 1.71 June 9, 2000
-119-
Functional Descriptions
ETC [ ETC ]
