EAGLE
PRELIMINARY
Ver 1.3
3.6.10 NAND Flash Memory ECC Code for LSN data (NFMECCL)
This register contains the NAND Flash memory ECC code for LSN data. A read operation to the NAND Flash Memory
ECC register clears this register.
Address : FFE0 1020h
P1_s~P4_s : Column Parity, P8_s~P16_s : Row Parity
Bit
31 : 16
15 : 8
R/W
R
R
Description
Default Value
Reserved
S_ECC1
-
FFh
(1, 1, 1, 1, 1, 1, ~P4_s, ~P4’_s)
7 : 0
R
S_ECC0
FFh
(~P2_s, ~P2’_s, ~P1_s, ~P1’_s, ~P16_s, ~P16’_s, ~P8_s, ~P8’_s)
* ~ : Logically inverse operation
3.6.11 NAND Flash Memory Configuration Register (NFMCFG)
This register contains the chip select signal and the CLE, ALE, WEx, REx time period.
Address : FFE0 101Ch
Bit
31 : 17
16
R/W
R
R/W
Description
Default Value
Reserved
-
1b
NAND Flash Memory Chip Select
0 : Chip Enable
1 : Chip Disable
15
R
Reserved
-
14 : 12
R/W
ALE/CLE Set-up Time (Ts)
111b
000 : 1 Clock 001 : 2 Clocks 010 : 3 Clocks 011 : 4 Clocks
100 : 5 Clocks 101 : 6 Clocks 110 : 7 Clocks 111 : 8 Clocks
Reserved
11
R
-
10 : 8
R/W
WEx Pulse Width (Twp)
111b
000 : 1 Clock 001 : 2 Clocks 010 : 3 Clocks 011 : 4 Clocks
100 : 5 Clocks 101 : 6 Clocks 110 : 7 Clocks 111 : 8 Clocks
Reserved
7
R
-
6 : 4
R/W
REx Pulse Width (Trp)
111b
000 : 1 Clock 001 : 2 Clocks 010 : 3 Clocks 011 : 4 Clocks
100 : 5 Clocks 101 : 6 Clocks 110 : 7 Clocks 111 : 8 Clocks
Reserved
3
R
-
2 : 0
R/W
ALE/CLE/CEx Hold Time (Th)
111b
000 : 1 Clock 001 : 2 Clocks 010 : 3 Clocks 011 : 4 Clocks
100 : 5 Clocks 101 : 6 Clocks 110 : 7 Clocks 111 : 8 Clocks
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
84
ETC [ ETC ]
