Ver 1.3
PRELIMINARY
EAGLE
3.6.7 NAND Flash Memory Operation Status Register (NFMSTAT)
This register reflects the operation status of NAND Flash memory.
Address : FFE0 1014h
Bit
31 : 5
4
R/W
R
R
Description
Default Value
Reserved
-
0b
NAND Direct Read Operation Completion bit
When NAND Direct Read operation is completed, this bit is set. This bit
is cleared by read.
3
R
NAND Internal Memory Write/Read Operation Completion
When internal memory transfer operation starts, this bit changes to 0.
This bit changes to 1 after transfer is completed.
1: Completion state.
1b
0: Transferring state
1
0
R
R
NAND Flash Memory Ready/Busyx Status
0 : NAND Flash Memory busy
1 : NAND Flash Memory Ready to operate
NAND Flash Memory Ready/Busyx Status
When Ready/Busyx signal changes from low to high, this bit becomes 1.
This bit is cleared by read.
0b
0b
3.6.8 NAND Flash Memory Low / High Start Address Register (NFMLSM / NFMHSM)
This register contains the higher and lower start address of internal memory for data transfer operation.
Address : FFE0 1024h / FFE0 102Ch
Bit
31 : 11
10 : 0
R/W
R
R/W
Description
Default Value
Reserved
-
Internal Memory(SRAM) Low Start Address /
Internal Memory(SRAM) High Start Address
000h
3.6.9 NAND Flash Memory ECC(Error Correction Code) Register(NFMECC)
This register stores the ECC code of NAND Flash Memory. This register is cleared automatically when it is read..
Address : FFE0 1018h P1~P4 : Column Parity , P8~P2048 : Row Parity
Bit
R/W
Description
Default Value
31 : 24
23 : 16
R
Reserved
-
R/Clear ECC2
(~P4, ~P4’, ~P2, ~P2’, ~P1, ~P1’, ~P2048, ~P2048’)
R/Clear ECC1
(~P1024, ~P1024’, ~P512, ~P512’, ~P256, ~P256’, ~P128, ~P128’)
R/Clear ECC0
(~P64, ~P64’, ~P32, ~P32’, ~P16, ~P16’, ~P8, ~P8’)
FFh
15 : 8
7 : 0
FFh
FFh
83
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
