EAGLE
PRELIMINARY
HcFmInterval
Ver 1.3
FFE0 5434h
FFE0 5438h
FFE0 543Ch
FFE0 5440h
FFE0 5444h
FFE0 5448h
FFE0 544Ch
FFE0 5450h
FFE0 5454h
FFE0 5458h
FFE0 5800h
FFE0 5804h
FFE0 5808h
FFE0 580Ch
FFE0 5810h
FFE0 5814h
FFE0 5818h
FFE0 581Ch
FFE0 5820h
FFE0 5824h
FFE0 5828h
FFE0 8000h
FFE0 8000h
FFE0 8000h
FFE0 8004h
FFE0 8004h
FFE0 8008h
FFE0 800Ch
FFE0 8014h
FFE0 8020h
FFE0 8020h
FFE0 8020h
FFE0 8024h
FFE0 8024h
FFE0 8028h
FFE0 802Ch
FFE0 8034h
FFE0 8040h
FFE0 8040h
FFE0 8040h
FFE0 8044h
FFE0 8044h
FFE0 8048h
FFE0 804Ch
FFE0 8054h
FFE0 8060h
FFE0 8060h
FFE0 8060h
FFE0 8064h
FFE0 8064h
FFE0 8068h
FFE0 806Ch
FFE0 8074h
FFE0 8C00h
FFE0 8C04h
FFE0 8C08h
FFE0 8C0Ch
FFE0 9400h
FFE0 9404h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
-
0h
0h
0h
0h
0h
0060h
0h
-
0h
0h
0h
0h
0h
0060h
0h
-
0h
0h
0h
0h
0h
0060h
0h
-
0h
0h
0h
0h
0h
0060h
0h
FFFFh
0h
-
HcFmRemaining
HcFmNumber
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
HcRhDescriptorB
HcRhStatus
Reserved
HcRhPortStatus[1]
Engine Control Register (YCICCON)
Y Buffer 0 Start Address Register (YCICYB0SA)
Y Buffer 1 Start Address Register (YCICYB1SA)
Y Buffer 2 Start Address Register (YCICYB2SA)
C Buffer 0 Start Address Register (YCICCB0SA)
C Buffer 1 Start Address Register (YCICCB1SA)
C Buffer 2 Start Address Register (YCICCB2SA)
Input Source Image X Size Register (YCICISXS)
Input Source Image Y Size Register (YCICISYS)
Output Image X Size Register (YCICOXS)
Output Image Y Size Register (YCICOYS)
UART Channel 0 Receiver Buffer Register (URB0)
UART Channel 0 Transmitter Holding Register (UTH0)
UART Channel 0 Divisor Latch LSB Register (UDL0)
UART Channel 0 Interrupt Identification Register (UII0 )
UART Channel 0 Divisor Latch MSB Register (UDLM0)
UART Channel 0 FIFO Control Register (UFCON0)
UART Channel 0 Line Control Register (ULCON0)
UART Channel 0 Line Status Register (ULSTAT0)
UART Channel 1 Receiver Buffer Register (URB1)
UART Channel 1 Transmitter Holding Register (UTH1)
UART Channel 1 Divisor Latch LSB Register (UDLL1)
UART Channel 1 Interrupt Identification Register (UII1)
UART Channel 1 Divisor Latch MSB Register (UDLM1)
UART Channel 1 FIFO Control Register (UFCCON1)
UART Channel 1 Line Control Register (ULCON1)
UART Channel 1 Line Status Register (ULSTAT1)
UART Channel 2 Receiver Buffer Register (URB2)
UART Channel 2 Transmitter Holding Register (UTH2)
UART Channel 2 Divisor Latch LSB Register (UDLL2)
UART Channel 2 Interrupt Identification Register (UII2)
UART Channel 2 Divisor Latch MSB Register (UDLM2)
UART Channel 2 FIFO Control Register (UFCCON2)
UART Channel 2 Line Control Register (ULCON2)
UART Channel 2 Line Status Register (ULSTAT2)
UART Channel 3 Receiver Buffer Register (URB3)
UART Channel 3 Transmitter Holding Register (UTH3)
UART Channel 3 Divisor Latch LSB Register (UDLL3)
UART Channel 3 Interrupt Identification Register (UII3)
UART Channel 3 Divisor Latch MSB Register (UDLM3)
UART Channel 3 FIFO Control Register (UFCON3)
UART Channel 3 Line Control Register (ULCON3)
UART Channel 3 Line Status Register (ULSTAT3)
Key Scan Control Register (KSCON)
YC Image
Capturer
UART
Key Scan Counter Register (KSCNT)
Key Scan Data Register 1 (KSD1)
Key Scan Data Register 2 (KSD2)
I2S Control Register (I2SCON)
Key Scan
I2S
0h
0h
I2S Mode Register (I2SMOD)
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
40
ETC [ ETC ]
