SLA7070MR, MPR/7071MR, MPR/7072MR, MPR/7073MR, MPR
■Internal Block Diagram
■Pin Assignment
Pin No.
Symbol
Function
1
2
3
4
Phase A output
Phase A output
OutA
OutA/
8
9
16 10 15
11
20 21 22 23
1
2
3
4
14
15
18
6
7
5
6
7
SenseA
N.C.
M1
Phase A current sense
N.C.
Reg
MIC
8
9
M2
Excitation mode/Sleep 2 setting input
Pre-
Driver
Pre-
Driver
Sequencer
&
Sleep Circuit
M3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Clock
Step Clock input
Protect
Protect
VBB
Driver supply (motor supply)
Device GND
Gnd
DAC
DAC
Ref/Sleep1
Control current mode/Sleep 1 setting input
Logic supply
+
–
+
V
DD
Synchro
Control
19
–
5
SenseA
SenseB
Reset
CW/CCW
Sync
Internal logic reset input
Normal/reverse control input
PWM control signal input
Protection circuit monitor output*1
Phase B current sense
PWM
Control
PWM
Control
R
S
OSC
RS
OSC
Flag
17
12
SenseB
OutB/
OutB
Phase B current output
Phase B current output
The protect circuit is deleted and the flag pin is N.C. for SLA7070MR, 7071MR, 7072MR, and 7073MR.
*1: N.C. pin for SLA7070MR, 7071MR, 7072MR, and 7073MR.
■Typical Connection Diagram
■External Dimensions (ZIP23 with Fin[SLA23Pin])
0.2
Vs=10V to 44V
31
0.2
24.4
0.2
4.8
0.2
16.4
0.1
1.7
Gate burr
3.2 0.15 × 3.8
φ
+
CA
Vcc=3.0V to 5.5V
OutA OutA
0.15
φ
3.2
BB
OutB OutB
VDD
C1
r1
0.2
Q1
2.45
Reset/Sleep1
Clock
(Measured at
the root)
SLA7070MR,MPR
SLA7071MR,MPR
SLA7072MR,MPR
SLA7073MR,MPR
CW/CCW
M1
4–(R1)
Micro-
computer,
etc.
M2
R-end
M3
Sync
N.C.
+0.2
–0.1
0.65
+0.2
0.55
–0.1
Flag
1
22 × P1.27 0.5 = 27.94
Ref/Sleep
0.7
SenseA
Gnd
SenseB
4.5
(Measured at the tip)
0.2
31.3
r2
r3
C2
(Including the resin burr)
One-point
Gnd
Forming No. No.2151
Logic Gnd
Power Gnd
Product Mass : Approx.6g
* There is no Flag pin (Pin-18) for SLA7070MR, 7071MR, 7072MR, and 7073MR.
ICs
101
ETC [ ETC ]
