DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Register Description
Register Address Register Name
Description
Basic Mode Control Register
Basic Mode Status Register
0
BMCR
BMSR
1
2
3
4
5
6
PHYIDR1
PHYIDR2
ANAR
ANLPAR
ANER
PHY Identifier Register #1
PHY Identifier Register #2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
DAVICOM Specified Configuration Register
DAVICOM Specified Configuration/Status Register
10Base-T Configuration/Status Register
Reserved For Future Use-Do Not Read/Write To These Registers
16
17
18
Others
DSCR
DSCSR
10BTCSR
Reserved
Key to Default
In the register description that follows, the default column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
(PIN#)
Value latched in from pin # at reset
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
20
Final
Version: DM9101-DS-F03
July 22, 1999
ETC [ ETC ]
