ADM7008
Function Description
During Read operation, a 2-bit turn around (TA) time spacing between the register
address field and data field is provided for the MDIO to avoid contention. Following the
turnaround time, a 16-bit data stream is read from or written into the MII management
registers of the ADM7008.
3.4.1 Preamble Suppression
The ADM7008 supports a preamble suppression mode as indicated by an 1 in bit 6 of the
basic mode status register (Register 1h). If the station management entity (i.e. MAC or
other management controller) determines that all PHYs in the system support preamble
suppression by reading a 1 in this bit, then the station management entity needs not
generate preamble for each management transaction. The ADM7008 requires a single
initialization sequence of 32 bits of preamble following powerup/hardware reset. This
requirement is generally met by pulling-up the resistor of MDIO. While the ADM7008
will respond to management accesses without preamble, a minimum of one idle bit
between management transactions is required as specified in IEEE 802.3u.
When ADM7008 detects that there is physical address match, then it will enable
Read/Write capability for external access. When neither physical address nor register
address is matched, then ADM7008 will tri-state the MDIO pin.
MDC
MDIO (MAC)
MDIO (PHY)
z
0
1
1
0
0
1
1
0
0
0
0
0
0
0
z
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
z
Opcode
(Read)
PHY Address
Register Address
Preamble
Start
TA
Register Data (16'h1300 in this Example)
(5'h0C in this example)
(5'h00 in this example)
Figure 3-23 SMI Read Operation
3.4.2 Reset Operation
The ADM7008 can be reset either by hardware or software. A hardware reset is
accomplished by applying a negative pulse, with duration of at least 200 ms to the RC pin
of the ADM7008 during normal operation to guarantee internal Power On Reset Circuit
is reset well. Software reset is activated by setting the reset bit in the basic mode control
register (bit 15, register 0h). This bit is self-clearing and, when set, will return a value of
1 until the software reset operation has completed, please note that internal SRAM will
not be reset during software reset.
MDC
MDIO (MAC)
z
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
z
Opcode
(Write)
PHY Address
Register Address
Preamble
Start
TA
Register Data (16'h1300 in this Example)
(5'h0C in this example)
(5'h00 in this example)
Figure 3-24 SMI Write Operation
ADMtek Inc.
3-25
ETC [ ETC ]
