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ADM7008 参数 Datasheet PDF下载

ADM7008图片预览
型号: ADM7008
PDF下载: 下载PDF文件 查看货源
内容描述: 八以太网10 / 100M PHY [Octal Ethernet 10/100M PHY]
分类和应用: 外围集成电路数据传输以太网局域网(LAN)标准时钟
文件页数/大小: 92 页 / 2746 K
品牌: ETC [ ETC ]
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ADM7008  
Function Description  
correlations between production and system testing. Baud rate Adaptive  
Equalizer/Timing Recovery compensates line loss induced from twisted pair and tracks  
far end clock at 125M samples per second. Adaptive Equalizer implemented with Feed  
forward and Decision Feedback techniques meet the requirement of BER less than 10-12  
for transmission on CAT5 twisted pair cable ranging from 0 to 140 meters.  
NRZI/NRZ and Serial/Parallel Decoder  
The recovered data is converted from NRZI to NRZ. The data is not necessarily aligned  
to 4B/5B code group’s boundary.  
Data Descrambling  
The descrambler acquires synchronization with the data stream by recognizing idle bursts  
of 40 or more bits and locking its deciphering Linear Feedback Shift Register (LFSR) to  
the state of the scrambling LFSR. Upon achieving synchronization, the incoming data is  
XORed by the deciphering LFSR and descrambled.  
In order to maintain synchronization, the descrambler continuously monitors the validity  
of the unscrambled data that it generates. To ensure this, a link state monitor and a hold  
timer are used to constantly monitor the synchronization status. Upon synchronization of  
the descrambler the hold timer starts a 722 us countdown. Upon detection of at least 6  
idle symbols (30 consecutive “1”) within the 722 us period, the hold timer will reset and  
begin a new countdown. This monitoring operation will continue indefinitely given a  
properly operating network connection with good signal integrity. If the link state  
monitor does not recognize at least 6 unscrambled idle symbols within 722 us period, the  
descrambler will be forced out of the current state of synchronization and reset in order to  
re-acquire synchronization.  
Symbol Alignment  
The symbol alignment circuit in the ADM7008 determines code word alignment by  
recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the  
descrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is  
aligned on a fixed boundary.  
Symbol Decoding  
The symbol decoder functions as a look-up table that translates incoming 5B symbols  
into 4B nibbles as shown in Table 3-1. The symbol decoder first detects the /J/K symbol  
pair preceded by idle symbols and replaces the symbol with MAC preamble. All  
subsequent 5B symbols are converted to the corresponding 4B nibbles for the duration of  
the entire packet. This conversion ceases upon the detection of the /T/R symbol pair  
denoting the end of stream delimiter (ESD). The translated data is presented on the  
internal RXD[3:0] signal lines with RXD[0] represents the least significant bit of the  
translated nibble.  
ADMtek Inc.  
3-4  
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