ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
5.6 DMA REGISTERS
Bit 3 = IM: End of block Interrupt Mask.
This bit is set and cleared by software.
0: No End of block interrupt request is generated
when IP is set
1: End of Block interrupt is generated when IP is
set. DMA requests depend on the DM bit value
as shown in the table below.
As each peripheral DMA channel has its own spe-
cific control registers, the following register list
should be considered as a general example. The
names and register bit allocations shown here
may be different from those found in the peripheral
chapters.
DM IM Meaning
DMA COUNTER POINTER REGISTER (DCPR)
Read/Write
Address set by Peripheral
A DMA request generated without End of Block
1
1
0
0
0
1
0
1
interrupt when IP=1
Reset value: undefined
A DMA request generated with End of Block in-
terrupt when IP=1
7
0
No End of block interrupt or DMA request is
generated when IP=1
C7
C6
C5
C4
C3
C2
C1
RM
An End of block Interrupt is generated without
associated DMA request (not used)
Bit 7:1 = C[7:1]: DMA Transaction Counter Point-
er.
Bit 2:0 = PRL[2:0]: Source Priority Level.
These bits are set and cleared by software. Refer
to Section 5.2 DMA PRIORITY LEVELS for a de-
scription of priority levels.
Software should write the pointer to the DMA
Transaction Counter in these bits.
PRL2 PRL1 PRL0 Source Priority Level
Bit 0 = RM: Register File/Memory Selector.
This bit is set and cleared by software.
0: DMA transactions are with memory (see also
DAPR.DP)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 Highest
1
2
1: DMA transactions are with the Register File
3
4
GENERIC EXTERNAL PERIPHERAL INTER-
RUPT AND DMA CONTROL (IDCR)
Read/Write
5
6
7 Lowest
Address set by Peripheral
Reset value: undefined
DMA ADDRESS POINTER REGISTER (DAPR)
Read/Write
7
0
Address set by Peripheral
Reset value: undefined
IP
DM
IM PRL2 PRL1 PRL0
7
0
Bit 5 = IP: Interrupt Pending.
This bit is set by hardware when the Trigger Event
occurs. It is cleared by hardware when the request
is acknowledged. It can be set/cleared by software
in order to generate/cancel a pending request.
0: No interrupt pending
A7
A6
A5
A4
A3
A2
A1
PS
Bit 7:1 = A[7:1]: DMA Address Register(s) Pointer
Software should write the pointer to the DMA Ad-
dress Register(s) in these bits.
1: Interrupt pending
Bit 4 = DM: DMA Request Mask.
Bit 0 = PS: Memory Segment Pointer Selector:
This bit is set and cleared by software. It is only
meaningful if DAPR.RM=0.
0: The ISR register is used to extend the address
of data transferred by DMA (see MMU chapter).
1: The DMASR register is used to extend the ad-
dress of data transferred by DMA (see MMU
chapter).
This bit is set and cleared by software. It is also
cleared when the transaction counter reaches
zero (unless SWAP mode is active).
0: No DMA request is generated when IP is set.
1: DMA request is generated when IP is set
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ETC [ ETC ]
